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| _florent_ | sajattack[m]: the XC7K325T boards could be interesting, but the nice thing with the Acorn is that it's a NiteFury: https://www.crowdsupply.com/rhs-research/nitefury, so already fully documented :) | 08:20 |
|---|---|---|
| zyp | oh, I didn't realize, that's nice | 08:23 |
| zyp | I also ordered one of those things yesterday | 08:24 |
| benh | _florent_: I orderd one :-) Do you know of some place that sells adapters M2 <-> female PCIe connector to use it as PCIe master ? | 08:24 |
| benh | or M2 <- > M2 | 08:24 |
| benh | _florent_: also what do you typically use to program it ? | 08:26 |
| _florent_ | benh: the issue when for using it as master will be the clocking, the adapter will need to generate the clock | 08:29 |
| _florent_ | benh: you could use traditional M2 to PCIe adapter and then connect the two PCIe boards using 2 USB3 to PCIe riser and a USB3 cable (that will swap the pairs) | 08:31 |
| benh | sounds ... messy :-) but ok | 08:32 |
| _florent_ | benh: but that's only for the PCIe lanes, you'll have to add the 100MHz clock. | 08:32 |
| benh | can't the Artix generate it ? | 08:32 |
| benh | that would be violating the slot standard but ... | 08:33 |
| benh | in the meantime, I'll probably need to sort out the jtag cable... what do you use for it ? custom made ? | 08:34 |
| benh | and do you get the UART out somewhere ? | 08:34 |
| zyp | it shouldn't be that hard to do a board with either two M.2 sockets or an M.2 and a pcie socket, cross routed plus a clock generator | 08:35 |
| benh | if you are a hw guy who has done boards in the past :) | 08:36 |
| benh | but I can probably find such quirky individuals around here :) | 08:37 |
| benh | paulus might be able to | 08:37 |
| benh | zyp: additionally such a board could provide power... it would be handy for a number of other things imho | 08:37 |
| benh | I was just wondering if such a thing already existed somewhere | 08:38 |
| _florent_ | benh: the jtag, you could use this https://www.digikey.com/product-detail/en/molex/0369200601/WM26622-ND/10233018 | 08:38 |
| tpb | Title: 0369200601 Molex | Cable Assemblies | DigiKey (at www.digikey.com) | 08:38 |
| _florent_ | to do a cable like this: https://www.eevblog.com/forum/fpga/sqrl-acorn-as-an-interesting-artix-7-board/msg3046402/#msg3046402 | 08:38 |
| tpb | Title: SQRL Acorn as an interesting Artix-7 board? - Page 2 (at www.eevblog.com) | 08:38 |
| _florent_ | and the same for the UART (in my case the UART was done over PCIe) | 08:39 |
| benh | yup, thx | 08:41 |
| benh | what USB jtag adapter do you guys favor these days ? | 08:46 |
| daveshah | Any generic FT2232H is good enough for 99% of stuff imo | 08:47 |
| benh | yup | 08:47 |
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| benh | _florent_: I assume you haven't had a chance to look at litedram_gen when using cpu "None" ? | 09:04 |
| benh | _florent_: If you can't, I'll try to spend some time this weekend understand how the SoC stuff got refactored and see if I can fix it | 09:05 |
| _florent_ | benh: not yet no sorry | 09:05 |
| benh | _florent_: btw, Paulus got Linux booting on microwatt :-) | 09:05 |
| benh | still hacks, esp since the toolchain basically assumes that powerpc64le has float & vectors | 09:05 |
| _florent_ | benh: great, using LiteDRAM? | 09:05 |
| benh | but he got it to busybox | 09:05 |
| benh | yup | 09:05 |
| benh | I've cleaned up my litedram adapter | 09:05 |
| benh | I now ship pre-generated cores and a script to re-generate so ppl dont' need to install Litex and don't have to deal with breakage when things change | 09:06 |
| benh | I'll send Anton a pull request soon | 09:06 |
| benh | doing a bit more testing | 09:06 |
| benh | _florent_: I also haven't had much time to dig again into pipelining the wishbone <-> native litedram interface | 09:07 |
| benh | that will be a good boost when I can do it | 09:07 |
| _florent_ | benh: i could try to help that; that would be easier if we get things working with ghdl-synth before to be able to simulate with litex_sim | 09:09 |
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| benh | yes, it would, I need to learn about it a bit | 09:22 |
| benh | Anton knows more but he is a bit scarce at the moment :) | 09:22 |
| benh | _florent_: btw, stupid vivado issue but you might know what it's about ... if I build with litedram disabled, I basically have the dram wires still in the xdc and the toplevel but I don't plumb them to anything | 09:55 |
| benh | _florent_: that leads to the following error in vivado | 09:55 |
| benh | ERROR: [DRC IOSTDTYPE-1] IOStandard Type: I/O port ddram_clk_n is Single-Ended but has an IOStandard of DIFF_SSTL135 which can only support Differential | 09:55 |
| benh | ERROR: [DRC IOSTDTYPE-1] IOStandard Type: I/O port ddram_clk_p is Single-Ended but has an IOStandard of DIFF_SSTL135 which can only support Differential | 09:55 |
| benh | interestingly it doesn't seem to complain about any other DIFF_SSTL135 wire | 09:55 |
| benh | any idea what that means ? | 09:55 |
| benh | ie, it's not complaining about dqs_p and dqs_n afaik | 09:57 |
| dkozel | My CLE-215+ have arrived. VRM heatsinks need to be reattached and I've ordered the JTAG cables. I haven't tried using an FT2232H (or similar) to load the FPGA and Flash, Sounds well worth a shot. | 10:01 |
| benh | _florent_: the weird thing is I'm pretty sure that used to work ... | 10:12 |
| _florent_ | benh: Vivado is probably considering it as single ended when not connected, the difference with the others DIFF signals is that clk is an output, the others are inouts | 10:15 |
| benh | _florent_: interestingly enough that used not to happen ... any suggestion on how to work around it without having separate toplevels ? | 10:32 |
| benh | _florent_: what would go wrong if I made it inout for example ? | 10:32 |
| _florent_ | benh: you can try to make it inout | 10:33 |
| benh | otherwise I'd have to hookup a differential buff of some sort right ? | 10:33 |
| daveshah | An OBUFDS with I connected to 0 would work | 10:34 |
| benh | yup, I was thinking of that, I just couldn't remember the name :) thx. I'll try that | 10:34 |
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| benh | _florent_: so I started having a look at "raw" sdram generation... the new structure makes it hard to completely take out the wishbone :) | 11:46 |
| benh | _florent_: you end up with self.bus = None in the SoC stuff and you have to add a lot of conditionals... a bit ugly | 11:46 |
| benh | _florent_: I suppose I could continue down that path, or make a dummy "bus" object that does nothing | 11:46 |
| benh | _florent_: one problem I haven't solved yet is exposing the CSRs... add_csr_master() is gone or replaced with something else ... digging | 11:47 |
| benh | _florent_: it gets really messy to remove the bus completely now :( | 11:50 |
| benh | _florent_: another approach would be to just leave a wishbone on top of the CSRs with just the CSRs on it and expose that to microwatt | 11:50 |
| benh | what do you reckon ? | 11:51 |
| benh | I tend to prefer less extraneous logic as we are trying to fit into the little arty and the core's growing... maybe I'll see about a dummy bus object | 11:53 |
| benh | no bus at all wreaks havoc with mem regions etc... | 11:53 |
| benh | I'm making progress with a dummy SoCBusHandler... now to get the CSR bus exposed... | 12:04 |
| somlo | so, 64-bit Litex+Rocket is now technically capable of self-hosting :) http://www.contrib.andrew.cmu.edu/~somlo/BTCP/LitexRocketSelfHosting.mp4 | 12:07 |
| somlo | here's the transcript if you don't feel like waiting for the (slow) video: http://www.contrib.andrew.cmu.edu/~somlo/BTCP/LitexRocketSelfHosting.log | 12:07 |
| benh | so CSR bus exposed... now to get CSRs in csr.h would be nice :) | 12:13 |
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| sajattack[m] | @somlo nifty | 12:18 |
| somlo | sajattack[m]: thanks :) Free-as-in-Freedom all-the-way-down (to the gateware) | 12:21 |
| somlo | now I need to make it faster before it's *useful*, but hey, that's a "simple matter of programming" :) | 12:22 |
| sajattack[m] | haha | 12:28 |
| sajattack[m] | would be curious to see how long it takes to synth and pnr, looks like you were bottlenecking on I/O | 12:39 |
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| somlo | loading things from the sdcard (over SPI) is slow. I guess I'll circle back on LiteSDCard, see what I can get away with once that starts working reliably | 12:57 |
| benh | _florent_: I think I'm getting there so don't bother about it until you start seeing patches from me, and then hopefully you won't puke :) | 12:58 |
| somlo | also, last time I checked, synth with yosys needed 1.3GB resident memory (on intel), and I only have 1GB on the trellisboard. I should refresh my toolchain and see if the latest and greatest somehow fits in a bit less RAM | 12:59 |
| Finde | benh: that is awesome about microwatt linux! are there any pics of the boot to share? | 13:14 |
| Finde | is there an irc channel or something for microwatt enthusiasts to gather on? :) | 13:15 |
| benh | Finde: not yet :) There's a slack but I don't know if it's public | 13:22 |
| benh | Finde: you can ask Mikey | 13:22 |
| benh | Michael Neuling <[email protected]> | 13:23 |
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| benh | At the last LCA we just got our icache and dcache, and at that point I discovered in horror that I had written about half of microwatt :) | 13:23 |
| benh | thankfully I got back to doing real work and Paul has been the busy bee since, adding a little MMU | 13:24 |
| benh | he's adding enough FP support now so that the core can do basic FP load/stores and we can emulate the rest in SW :) | 13:24 |
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| Finde | hahaha | 14:01 |
| benh | _florent_: hrm... sdram.c now depends on the LiteX timer being there.. that's rather ... annoying :) | 14:57 |
| zyp | somlo, I'm tempted to do an ecp5 board with a sodimm socket, to make a cheap design with lots of ram | 14:57 |
| zyp | partly because it'd be cool to have a design that can synthesize itself | 14:58 |
| benh | _florent_: I might try to hid that behind a simple abstraction... | 14:58 |
| benh | _florent_: not just for standalone microwatt inits, but also bcs even if run in LiteX, microwatt doesn't really need/want that external timer | 14:58 |
| benh | powerpc has an architected timebase & decrementer facility in the core | 14:59 |
| somlo | zyp: I was told it's supposed to be a fiddly endeavor, with lots of trial-and-error, getting all the traces "just right" to a sodimm | 15:07 |
| somlo | but if you pull it off, I'll definitely want to put in for a batch of 5-10 of such boards :) | 15:08 |
| somlo | ideally, I'd like to see the trellisboard (https://github.com/daveshah1/TrellisBoard) modded to support a sodimm socket | 15:11 |
| tpb | Title: GitHub - daveshah1/TrellisBoard: Ultimate ECP5 development board (at github.com) | 15:11 |
| somlo | disclaimer: I have zero skill designing PCBs, so this is just me flapping my gums at this point :D | 15:12 |
| benh | anything powered off the same USB that does FTDI JTAG & UART will rock for me :) | 15:13 |
| benh | ideally with PCIe *host* as well ... hehe | 15:13 |
| benh | I can't design PCBs for the life of me... 4 decades doing SW, I just skimmed some HW design skills off colleagues over the year, just enough to hack FPGAs a bit but don't let me go anywhere near anything analog :) | 15:14 |
| zyp | somlo, to me, routing a sodimm socket looks easier than routing to soldered ICs | 15:14 |
| zyp | the challenge is that a sodimm is 64-bits wide | 15:15 |
| benh | an M2 connector would do for PCIe as well | 15:15 |
| benh | zyp: aren't there "interesting" issues with trace lenght ? | 15:15 |
| somlo | benh: I think I see where you're going with pci host: plant the fpga dev board into something like this: https://www.onestopsystems.com/product/cube2-metal-expansion-enclosure-5-pcie-slots | 15:16 |
| tpb | Title: CUBE2 METAL expansion enclosure, 5 PCIe slots | One Stop Systems (at www.onestopsystems.com) | 15:16 |
| zyp | as far as I can tell, it'll need IO from both left and right side banks to get enough DQS groups, which makes clocking the design more challenging | 15:16 |
| somlo | and have support for off-the-shelf peripherals, like a regular pc motherboard, except with a risc-v cpu and northbridge | 15:16 |
| zyp | but ecp5 has an «edge clock bridge» which apparently is supposed to solve that | 15:17 |
| benh | somlo: well, I want a way to get PCIe master, anything will do | 15:17 |
| zyp | so it might work :) | 15:17 |
| benh | M2 female, PCIe female etc... | 15:17 |
| benh | that way you can stick an M2 for storage | 15:17 |
| benh | or a cable card to an external expansion for more stuff | 15:17 |
| benh | and get real IOs | 15:17 |
| benh | but that's the guy who use to work on server chips talking so .... :) | 15:17 |
| somlo | zyp: all I can do is say encouraging stuff, cheer you on, and kibbitz from the sidelines until you have something that works, but it WOULD rock if you pulled it off! :) | 15:18 |
| benh | but once you have the host connector, the sky's the limit. From just a local nvme M2 or wifi to bridges with sockets etc... | 15:18 |
| benh | well, if it looks like it's going to rock enough for me I can chip some $ in too | 15:18 |
| benh | (mind you personal hobby $, so you won't get rich) | 15:18 |
| benh | maybe some friends might too | 15:19 |
| benh | At some stage I might try to tweak microwatt into a 32-bit cpu I can run old MacOS on :) | 15:19 |
| benh | though not before Paulus gets an FPU going :) | 15:19 |
| benh | anyway, I'm way out of topic for the channel, sorry guys :) Friday night .... | 15:20 |
| somlo | benh: oh, cool, it's Friday... totally forgot ;) | 15:20 |
| benh | well it's Sat. already here :) | 15:20 |
| benh | oh btw, now that I have some experienced ppl around ... | 15:21 |
| benh | one issue I've been seeing with microwatt when I use litedram (which might relate to sourcing the clock from litedram's pll rather than our old clock generator) | 15:21 |
| sajattack[m] | there's a different connector for pcie host and device? | 15:21 |
| benh | the UART output is crappola for a few hundred milliseconds | 15:21 |
| benh | so the first messages out of the core are garbled | 15:22 |
| benh | if I put a wait loop before outputing things, it's fine | 15:22 |
| benh | it looks like the clocks aren't rigght for some amount of time despite the PLL being locked | 15:22 |
| benh | but it could be something else too... | 15:23 |
| benh | sajattack[m]: well... yes and no ... | 15:23 |
| benh | PCIe is symetrical P2P mostly | 15:23 |
| benh | but someone has to provide the clock and power | 15:23 |
| sajattack[m] | oh ok | 15:23 |
| benh | and I yet have to see a base board that provides power, has an M2 female, and wires that to a PCIe female connector (or another M2 female) :) | 15:24 |
| benh | so far the best idea is _florent_'s (iirc) to use cable cards and swap wires | 15:24 |
| benh | (the ones that use a USB cable) | 15:24 |
| sajattack[m] | yeah I was talking with my friend about the board florent discovered and he said it would be possible to do stuff like take over the audio card in a pc and make a synth and stuff | 15:24 |
| sajattack[m] | bit overkill for a synth but the concept I mean | 15:25 |
| sajattack[m] | taking over random pc peripherals | 15:25 |
| sajattack[m] | which didn't jive with what you were saying about a different connection in my mind | 15:25 |
| sajattack[m] | but I get it now | 15:25 |
| benh | well, if somebody is good at doing PCBs it shouldn't be hard to do something like that | 15:26 |
| benh | a base board with M2 female connector, power, and a PCIe female socket | 15:26 |
| benh | we could probably get away with generating the clock from the Artix, not sure there | 15:26 |
| zyp | benh, or just put a clock on it | 15:27 |
| sajattack[m] | if you like it then you shoulda put a clock on it | 15:27 |
| sajattack[m] | I was talking about just sticking the nvme on the cler? board in a pc | 15:29 |
| benh | zyp: yup... PCIe is 100Mhz oscillator right ?\ | 15:29 |
| sajattack[m] | and hijacking things | 15:29 |
| benh | allright, off to bed.. | 15:29 |
| _florent_ | somlo: nice self hosting demo, glad you manage to get all the pieces working! (now it would indeed need to be faster :)) | 17:42 |
| _florent_ | benh: even with a board as PCIe endpoint, if Bus mastering is enabled, you can already do interesting things in the system from the board. LitePCIe only support Endpoint for now, adding Root support should not be too complicated (the lower layers could probably be reused), but it's still a bit of work/testing | 17:46 |
| somlo | _florent_: thanks, now my OCD will finally allow me to focus on other things (like maybe reconciling the spi-master gateware and linux driver at bpw > 8bit) :) | 18:16 |
| somlo | and studying the ecp5 oddr added-delay impact on litesdcard -- that's probably the best chance I have to get faster storage... | 18:18 |
| Skip | _florent_: Just FYI the May 5 commit to linux-on-litex-vexriscv "buildroot/linux.config: enable SMP" broke Linux on the pano_logic_g2 platform. | 18:24 |
| Skip | _florent_: I rolled back to May 1 " conda/requirements.txt: add required pythondata repositories." and that fixed it. | 18:24 |
| Skip | The kernel booted, but hung after init was started. | 18:25 |
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| _florent_ | Skip: ok thanks, i'll look at this | 19:19 |
| zyp | _florent_, is the DMA stuff in litepcie based on bus mastering? | 20:16 |
| zyp | apologies if that's a stupid question, I'm not very familiar with pcie yet :) | 20:16 |
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| _florent_ | zyp: yes it's done using bus mastering | 20:29 |
| zyp | it'll be interesting to delve into once I get that acorn board | 20:34 |
| zyp | I don't have anything suitable to plug that into, so I went ahead and ordered one of these as well: https://www.seeedstudio.com/ODYSSEY-X86J4105864-p-4447.html, looked like a nice board for experimenting with this stuff :) | 20:35 |
| tpb | Title: Seeed Studio Bazaar, Boost ideas, Extend the Reach (at www.seeedstudio.com) | 20:36 |
| zyp | I think the only m.2 slot I've got in the house at the moment is in my wife's computer, and I don't think she'd appreciate me messing with that | 20:37 |
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| futarisIRCcloud | If anyone is after a cheap x86 host system with mPCIe slots, I can recommend the APU2 series. https://www.pcengines.ch/apu2.htm . There is also good coreboot support on these. | 22:12 |
| tpb | Title: PC Engines apu2 system boards (at www.pcengines.ch) | 22:12 |
| futarisIRCcloud | Has anyone made any breakout boards for the DF52 connectors on the NiteFury / Acorn CLE-215+ ? | 22:18 |
| zyp | I figured I'll just make a breakout cable assembly | 22:19 |
| zyp | DF52 in one end, header sockets in the other | 22:19 |
| zyp | those apu2 boards looks cute, but they'd be more interesting if they had m.2 | 22:39 |
| dkozel | the ODYSSEY board from Seeedstudio looks cool | 22:41 |
| dkozel | still hoping to get a Thunderbolt 3 to m.2 adapter :) | 22:43 |
| dkozel | Or USB 3.{1,2} to m.2 as consolation prize | 22:44 |
| zyp | all the onboard IO looks convenient too, I figure I can use those to hook up the jtag port of the acorn | 22:45 |
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| zyp | I believe openocd can already use sysfs gpio, but I guess that'd be fairly slow, so I guess the onboard microcontroller can do well as a jtag adapter | 22:47 |
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| futarisIRCcloud | https://www.eevblog.com/forum/fpga/sqrl-acorn-as-an-interesting-artix-7-board/ | 23:17 |
| tpb | Title: SQRL Acorn as an interesting Artix-7 board? - Page 1 (at www.eevblog.com) | 23:17 |
| futarisIRCcloud | mPCIe can be converted to m.2. I'm sure there's a cheap converter or two online somewhere... | 23:20 |
| zyp | mpcie is only one lane IIRC | 23:21 |
| futarisIRCcloud | For thunderbolt 3 to m.2, I thought someone was doing that with PCILeech FPGA. | 23:24 |
| futarisIRCcloud | https://github.com/ufrisk/pcileech-fpga | 23:24 |
| tpb | Title: GitHub - ufrisk/pcileech-fpga: FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software (at github.com) | 23:24 |
| zyp | yeah, there are thunderbolt to m.2 adapters around | 23:25 |
| zyp | e.g. https://www.aliexpress.com/item/4000557577340.html | 23:26 |
| tpb | Title: Intel Certified USB C Thunderbolt 3 NVME SSD Enclosure Type C Case M Key NVMe connector Excellent Dissipation for Window Mac OS|HDD Enclosure| - AliExpress (at www.aliexpress.com) | 23:26 |
| zyp | but there's also usb3 to m.2 adapters around, which looks similar from the outside (just a usb-c port), but wouldn't work for generic pcie | 23:28 |
| zyp | looked a bit into that earlier, and the latter commonly seems to be based on ASM2362, which does usb3 mass storage to pcie nvme | 23:29 |
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