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| Dolu | benh: Hi, i'm working on VexRiscv SMP. About the SMP stuff / DMA coherency, basicaly, VexRiscv SMP is based on write-through invalidate L1 D$ | 00:14 |
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| Dolu | So, each CPU has a invalidation port, to make the DMA coherent, i was thinking about snooping all DMA writes to invalidate all the CPU related cache line, so seem similar to your idea isn't it ? | 00:16 |
| Dolu | But about the sync stuff, i think that's a bit different, basicaly the invalidation bus is as following : | 00:17 |
| Dolu | 3 Streams : inv stream to request invalidation (interconnect -> CPU), ack stream to notify the invalidation is effective (CPU -> interconnect), sync stream to notify the master who produce the invalidation that it is done and coherent. (interconnect -> CPU) | 00:20 |
| Dolu | Basicaly, the DMA can be seen as a proper "HART", my idea was that a CPU can ask the DMA to issue a fence (so basicaly, waiting that all pending sync are done) | 00:24 |
| Dolu | Or maybe the DMA should just simply not consider a memory job done until all the modified memory is consistant ? | 00:24 |
| Dolu | But honestly i do not have much experiences into SMP systems XD, so i might say bullshit. | 00:28 |
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| scanakci | is it possible to have ethernet support without depending on any external interrupts? I saw this discussion and looks like it is possible (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/13). I just wanted to make sure that I am not misinterpreting something. | 02:55 |
| tpb | Title: Integrate LiteEth · Issue #13 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 02:55 |
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| futarisIRCcloud | scanakci: Polling works (slowly). | 04:52 |
| scanakci | thanks @futarisIRCcloud. | 05:28 |
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| benh | Dolu: hey | 09:05 |
| benh | Dolu: not sure you need to notify the master per-se... | 09:06 |
| benh | Dolu: Ideally you want to synchronize the control path to the master with the DMA path, so if you really have completely separate "busses" | 09:07 |
| benh | Dolu: you could have something like the MMIO reads by the CPU from that master would have their response held until previous invalidations by that master have completed | 09:07 |
| benh | not necessarily *all* invalidations, just previous ones | 09:07 |
| benh | but there are many different ways ... the MMIO orderingg method is just the most common | 09:08 |
| benh | if you really don't want to go down that path, and prefer just notifying the master, then you can have a status reg that the CPU can read to check that pending DMAs have completed | 09:08 |
| benh | but it's impractical as the master could already be writing data for a different packet | 09:08 |
| benh | anyway, food for thoughts... | 09:09 |
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| Dolu | benh: Hi ^^ What do you mean by 'per-se' ? | 20:47 |
| futarisIRCcloud | https://twitter.com/enjoy_digital/status/1257985111469015040 | 21:28 |
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| sajattack[m] | too cool | 22:43 |
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| benh | That looks amazing ! I just ordered one :) | 23:17 |
| benh | now the question is ... is there such a thing as an M2 slot to PCIe slot that allows to use that thing as a PCIe master :) | 23:20 |
| sajattack[m] | how about them apples https://www.ebay.ca/itm/XC7K325T-2FFG900C-XC7K325T-2FFG676I-IC-FPGA-900FPGA-BGA676Good-for-Mining/323639890046?hash=item4b5a70d07e:g:p6IAAOSwDmxcNBGk | 23:30 |
| tpb | Title: XC7K325T-2FFG900C XC7K325T-2FFG676I IC FPGA 900FPGA BGA676Good for Mining | eBay (at www.ebay.ca) | 23:30 |
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