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| shuffle2 | from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII causes liteeth\phy\__init__.py to run, which will import a bunch of random things for platforms i'm not targeting :/ | 00:37 |
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| shuffle2 | is there something equivalent to settings64-Vivado.bat for lattice diamond? i've only used the tcl console. or is just adding lattice bin paths to PATH the "proper" way (it does seem to be working..)? | 00:44 |
| shuffle2 | curious why ecp3 support was removed :/ | 00:48 |
| futarisIRCcloud | https://youtu.be/F613zbxi03E | 01:02 |
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| shuffle2 | litex\boards\platforms\versa_ecp5.py imports LatticeProgrammer but never uses it? | 01:46 |
| shuffle2 | are you even supposed to use create_programmer()? only see it used in one place | 01:56 |
| xobs | shuffle2: that's an excellent question. I've never actually used the programmer myself. that sounds like some vestigial import taht could probably be removed. | 02:06 |
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| shuffle2 | lol, the pgrcmd tool in diamond tries to import some c++ symbol from vmcontrol.dll with type mismatch, so it fails -.- | 02:40 |
| shuffle2 | heh, the pgrcmd from the standalone package imports the correct symbol...wonder how they mixed that up | 02:51 |
| shuffle2 | what litex calls versa_ecp5 is actually versa_ecp5g ? :( | 03:00 |
| shuffle2 | very cool to see icmp just work tho :D | 03:25 |
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| _florent_ | scanakci: nice for Linux on BlackParrot, for the simulation, are you using a simulated SRAM or LiteDRAM + DFI model (--with-sdram), the latter could allow you to be closer to the actual hardware behavior if that's not what you are already using. | 07:08 |
| _florent_ | shuffle2: there are probably indeed a few points we could improve (imports, programmers, etc...) happy to have issues or PR regarding that, i was planning working on improving programmers soon to have something more coherent | 07:10 |
| _florent_ | shuffle2: otherwise for ECP | 07:10 |
| _florent_ | ECP3, i was not aware of anyone using it, so removed ECP3 support since ECP5 seems now a better choice: easier to source, probably cheaper and has an open-source toolchain, etc... | 07:12 |
| _florent_ | but we could re-introduce it if you think this is useful | 07:13 |
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| scanakci | _florent_: I use --ram-init option. I guess it refers to the former one. | 08:03 |
| scanakci | In litex_sim, how should my command line look like if I use --with-sdram option? With ram-init option, I specify my bbl in the command line easily but could not realize how I can specify my bbl if I use --with-sdram. | 08:06 |
| scanakci | it looks like that there is --sdram-init option in the latest version. My LiteX version does not have it. I guess it is time to upgrade my LiteX repo. | 08:11 |
| _florent_ | scanakci: you can also initialize the memory with --with-sdram by using --sdram-init | 08:12 |
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| somlo | _florent_: any idea how much ddr3 the ECPiX-5 board is expected to have on board? | 19:28 |
| Finde | readme here suggests 512MB: https://github.com/litex-hub/linux-on-litex-vexriscv | 19:47 |
| tpb | Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com) | 19:47 |
| somlo | Finde: thanks! | 20:12 |
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| dkozel | _florent_: FYI the Aller PCIe image (just rebuilt with all latest toolchain code) is running | 21:58 |
| dkozel | LnkSta:Speed 5GT/s (ok), Width x4 (ok) | 21:58 |
| dkozel | DMA_SPEED(Gbps) TX_BUFFERS RX_BUFFERS DIFF ERRORS | 22:00 |
| dkozel | 8.35 25599 25471 128 0 | 22:00 |
| dkozel | Good for ~130 Megasamples / second in GNU Radio/Numpy's complex 32 bit float format. Yep, I can work with that! | 22:02 |
| shuffle2 | _florent_: re: ecp3, probably not a big deal...i'm porting an old project from ecp3 to ecp5(non-5g) and would be nice to have both targets working at once, but i can just add the ecp3 stuff locally...needed to tweak some stuff for non-5g also anyway | 22:02 |
| shuffle2 | unrelated general litex question: why does litex contain a lot of duplicated + modified migen/misoc classes? (the target platform definitions, things in soc/interconnect, etc) | 22:04 |
| zyp | maybe it's easier to maintain a modified copy than to get changes upstreamed? | 22:14 |
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| dkozel | Does anyone know of a "blank" or basic LiteX submodule template showing how to setup a wishbone interface (maybe a loopback?) and a register inside the module? | 23:05 |
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| sajattack[m] | the bitbang module is pretty basic https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/bitbang.py | 23:37 |
| tpb | Title: litex/bitbang.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:37 |
| sajattack[m] | it does registers, but not wishbone | 23:37 |
| sajattack[m] | https://github.com/enjoy-digital/litex/blob/5ef869b9ebdcbfbe037e1fee6a06866a2837a168/litex/soc/cores/i2s.py#L123 this does wishbone but the surrounding code is more confusing | 23:39 |
| tpb | Title: litex/i2s.py at 5ef869b9ebdcbfbe037e1fee6a06866a2837a168 · enjoy-digital/litex · GitHub (at github.com) | 23:39 |
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