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| mithro | Skip: Thanks for all your work on the Pano stuff! | 17:38 |
|---|---|---|
| mithro | Skip: Did you see the work that Charles is doing on VexRISCV SMP? | 17:38 |
| mithro | Skip: I added two issues to https://github.com/skiphansen/panog2_linux that I think you should look into | 18:06 |
| tpb | Title: GitHub - skiphansen/panog2_linux: Prebuilt images for Linux for the Pano Logic G2 (at github.com) | 18:06 |
| john_k[m] | the VexRISCV SMP email is exciting | 18:09 |
| john_k[m] | is there info anywhere on how to use buildroot to compile the kernel / rootfs for linux-on-litex-vexriscv? | 18:29 |
| john_k[m] | I tried the typical buildroot `make BR2_EXTERNAL=/home/dev/Code/linux-on-litex-vexriscv/buildroot/ menuconfig` but it doesn't pick anything up, I see BR2_EXTERNAL_LITEX_VEXRISCV_PATH mentioned in external.mk but it's not obvious where that should point to as `package` directory doesn't exist in the linux-on-litex-vexriscv dir | 18:33 |
| john_k[m] | ah setting it also to the same dir and then manually loading the vexriscv defconfig works, needed to also manually create a .config symlink after the menuconfig | 18:39 |
| john_k[m] | if someone could sanity check how I'm invoking that, i'll issue a PR to the readme | 18:45 |
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| Skip | mithro: No I hadn't noticed Charle's VexRISCV SMP ... my mind was blown enough with one processor! | 19:54 |
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| mithro | john_k[m]: Sending a PR to the readme would be great! | 19:55 |
| mithro | Skip: With how huge the panologic FPGA is, the issue is almost certainly going to be memory bandwidth | 19:55 |
| shuffle2 | i'd like to use liteEth on lattice, and uart, whereever that lives. but i'm on windows, and dont really want to run the litex_setup.py script...is there a less hueg/gross way to use this subset? i've already used migen for other stuff, just not litex | 19:56 |
| mithro | We could probably do like a 32 way complex pretty easily | 19:56 |
| Skip | mithro: and 1/2 of the SDRAM isn't be used yet... | 19:56 |
| mithro | Skip: kgugala was working on that | 19:56 |
| Skip | Cool! | 19:57 |
| mithro | shuffle2: You can just use them like any other Python module, but you need to make sure to update everything when you do | 19:57 |
| john_k[m] | mithro: oh? interesting! | 19:57 |
| mithro | shuffle2: A virtualenv and litex_setup.py works pretty well | 19:58 |
| mithro | john_k[m]: https://github.com/enjoy-digital/litedram/pull/157 and https://github.com/enjoy-digital/litex/pull/411 | 19:58 |
| tpb | Title: Support for multiple SDRAM PHYs in single SoC by mglb · Pull Request #157 · enjoy-digital/litedram · GitHub (at github.com) | 19:58 |
| mithro | john_k[m]: (More I should say kgugala has someone working for him looking into it.) | 19:59 |
| mithro | john_k[m] / Skip: https://github.com/timvideos/litex-buildenv/wiki/Linux | 20:01 |
| tpb | Title: Linux · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 20:01 |
| john_k[m] | I'll have to hook my Pano2 back up once I'm done with some ULX3s work | 20:07 |
| john_k[m] | looks like some great progress has been mad | 20:07 |
| john_k[m] | * looks like some great progress has been made | 20:07 |
| zyp | shuffle2, you could also just add them to pythonpath and import them as is | 20:08 |
| zyp | I have a deps/ directory with migen, litex and the other lite* repos checked out as git submodules and an __init__.py that reads like this: https://paste.jvnv.net/view/Fp5KI | 20:12 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 20:12 |
| zyp | so all I have to do is import deps to add all the other stuff to pythonpath before I import anything else | 20:13 |
| mithro | There is also @xobs has https://github.com/xobs/lxbuildenv which kind of works like that | 20:14 |
| tpb | Title: GitHub - xobs/lxbuildenv: Simplified environment for litex (at github.com) | 20:14 |
| john_k[m] | zyp: I've been using https://github.com/xobs/lxbuildenv/ to something very similar | 20:15 |
| tpb | Title: GitHub - xobs/lxbuildenv: Simplified environment for litex (at github.com) | 20:15 |
| john_k[m] | hah, didn't see your post as I was typing that mithro | 20:15 |
| zyp | ah, yeah, that looks pretty similar | 20:17 |
| shuffle2 | zyp: nice. yea, that's how i currently use migen | 20:36 |
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| scanakci | https://usercontent.irccloud-cdn.com/file/6XD19pGl/Linux-Bootup%20using%20Uart%20(Simulation) | 21:02 |
| scanakci | The simulation works fine after integrating LiteX Uart. | 21:03 |
| mithro | sajattack[m]: Congratulations! | 21:03 |
| sajattack[m] | what? | 21:03 |
| mithro | Opps | 21:03 |
| scanakci | FPGA is still causing the same issue :( | 21:04 |
| mithro | s/sajattack[m]/scanakci/ | 21:04 |
| sajattack[m] | lol | 21:04 |
| scanakci | https://usercontent.irccloud-cdn.com/file/qU1rxOqY/FPGA-bootup.png | 21:04 |
| scanakci | thanks Tim :) | 21:04 |
| sajattack[m] | oh nice | 21:05 |
| sajattack[m] | I was looking into blackparrot | 21:05 |
| sajattack[m] | how does it compare to vexriscv? | 21:05 |
| scanakci | @sajattack[m] : I do not have any experience with vexriscv. Once I boot up Linux on FPGA, I will try to compare BP with Rocket and potentially Vex. | 21:06 |
| scanakci | According to bbl dump, the PC value where trap happens is a li a2,24 https://usercontent.irccloud-cdn.com/file/A8yrFSSR/bbldump%2C%20failing%20PC | 21:07 |
| scanakci | I also printed the opcode (msr_read(mbadaddr)) which is adba2acf. Not sure where this opcode comes from. I printed the memory starting from 0x8000_0000 until end of bbl in trap function. It seems legit (i.e. matches with bbl dump and does not contain weird opcode) | 21:10 |
| scanakci | https://forums.sifive.com/t/bbl-debugging-using-gdb/2324/6 | 21:11 |
| tpb | Title: Bbl debugging using gdb - Freedom U500 - SiFive Forums (at forums.sifive.com) | 21:11 |
| sorear | missing a fence.i somewhere and reading garbage from the i$? | 21:13 |
| scanakci | This guy had a similar issue. He noticed that bss area was not clear before the boot-up. bss size looks 0 byte in my case so I do not think this is the problem. However, it tells me that illegal instruction trap may be misleading here. | 21:13 |
| daveshah | Does it fail exactly the same way each time? | 21:13 |
| scanakci | @daveshah yes it is deterministic | 21:14 |
| scanakci | @sorear would not it cause issues on Simulation too? | 21:14 |
| sorear | you mean spike/etc or verilator/etc? | 21:15 |
| scanakci | verilator | 21:16 |
| daveshah | Deterministic is good, that significantly reduces the likelihood that its something like marginal DDR3 or timing | 21:17 |
| sorear | maybe change something unrelated in a lower-address function to perturb the addresses, and see what changes? | 21:18 |
| scanakci | will give it a shot | 21:19 |
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