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| pdp7 | _florent_: any thoughts on how to handle different dummy bytes for old versus new Arty board? | 17:38 |
|---|---|---|
| mithro | _florent_: https://github.com/enjoy-digital/litex/issues/394 | 18:11 |
| tpb | Title: RFC: Split LiteX CPU cores into their own Python modules · Issue #394 · enjoy-digital/litex · GitHub (at github.com) | 18:11 |
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| Claude | Oh? Microwatt is supported in LiteX ? Is there a way to feed trellis/yosys vhdl from within LiteX ? With ghdl-synth ? | 19:11 |
| _florent_ | Claude: this is not fully finished: https://github.com/enjoy-digital/litex/issues/245 | 20:05 |
| tpb | Title: Import the microwatt PowerPC core · Issue #245 · enjoy-digital/litex · GitHub (at github.com) | 20:05 |
| _florent_ | the software support needs to be finished/debug, but it's already possible to implement it in a SoC with vendor tools | 20:06 |
| _florent_ | the idea is to use ghdl-synth yes for the simulation with litex_sim and yosys/nextpnr | 20:07 |
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| sajattack[m] | what speed sdram do I need for a 640x480 framebuffer? | 22:26 |
| sorear | what refresh rate and color depth do you want? | 22:45 |
| sajattack[m] | 60hz and 32bit | 22:53 |
| sajattack[m] | I don't need 32bit but I don't know how to make litex do less than 32bit so... | 22:53 |
| sajattack[m] | overclocking my pixel clock seems to help | 22:58 |
| sajattack[m] | dunno why | 22:58 |
| sajattack[m] | I gotta run it at 2.34x to get the expected hsync | 23:01 |
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