Wednesday, 2020-02-19

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awygle_florent_: is there documentation of how litex streams are intended to work, other than the source file? (i'm continuing to investigate a design for nmigen streams)01:09
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somlo_florent_: so, tomorrow when I'm back in the office I'll try specifying ClockSignal("clk100") explicitly, since I just realized I can do that :)03:27
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_florent_awygle: sorry, there are not that much information, the basis is what i described in https://github.com/nmigen/nmigen/issues/317#issuecomment-583277029, so a Record of signal very similar to a simplified AXI that forms an Endpoint08:32
tpbTitle: Stream Abstraction for nmigen.lib · Issue #317 · nmigen/nmigen · GitHub (at github.com)08:32
_florent_each module then has sink(s) and source(s) that you connect together with self.comb += module0.source.connect(module1.sink)08:33
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acathlaI just found the right board definition file in... migen : migen/build/platforms/ice40_up5k_b_evn.py, but not in litex nor litex-boards10:21
_florent_acathla: if you look for a board in addition to litex-boards you can look at  https://github.com/m-labs/migen/tree/master/migen/build/platforms and https://github.com/timvideos/litex-buildenv/tree/master/platforms, you should be able to reuse it almost directly. The ones in litex-boards are the ones that have been contributed by LiteX developers that are tested with LiteX.11:06
tpbTitle: migen/migen/build/platforms at master · m-labs/migen · GitHub (at github.com)11:06
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acathlaInfo:          ICESTORM_LC: 76070/ 7680   990%13:59
acathlawhen I try to add LiteEthMAC to my design (when adding the self.add_wb_slave() about that ethmac)14:01
acathlaWhat could cause that?14:02
_florent_hmm, this is probably the SRAMs of the MAC that are implemented as logic, what's the resource usage without LiteEthMAC?14:14
acathla_florent_, ICESTORM_LC:  1020/ 7680    13%14:36
acathla_florent_, I just see some FIFOs I can reduce a bit14:38
acathlaand ICESTORM_RAM:     1/   32     3% without LiteEthMAC14:40
acathlaICESTORM_RAM:     9/   32    28% with it14:40
pdp7_florent_: thanks for the response about JTAG on the arty.  I'm trying it out now.  This is the first time I've used this Arty.  Only other experience was mithro walked me through litex-buildenv on an Arty at FOSDEM15:26
pdp7I'm following "Installing OpenOCD (only needed for hardware test)" now from linux-on-litex-vexriscv15:27
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_florent_acathla: i could look if you are able to share your design17:31
_florent_acathla: or you can create an issue with the files to reproduce on LiteX or LiteEth17:32
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pdp7_florent_: i'm trying to get my system to build arty17:48
pdp7./make.py --board=arty --build17:48
pdp7ends in this error17:48
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pdp7oops bad pasting17:49
pdp7I think the issue is:17:49
pdp7/home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/Vivado/2017.3/bin/rdiArgs.sh: line 179: 29301 Segmentation fault      (core dumped) "$RDI_PROG" "$@"17:49
pdp7but I am not sure what RDI is17:49
_florent_pdp7: that's strange, have you already been able to build a design with your installed version of Vivado?17:53
pdp7I was able to do it with litex-buildenv17:54
_florent_could you try building https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/arty.py?17:54
tpbTitle: litex/arty.py at master · enjoy-digital/litex · GitHub (at github.com)17:54
pdp7https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode#resuming-development17:54
tpbTitle: HowTo LCA2018 FPGA Miniconf VexRiscv Renode · timvideos/litex-buildenv Wiki · GitHub (at github.com)17:54
pdp7I'm doing:17:54
pdp7pdp7@x1:~/dev/enjoy/linux-on-litex-vexriscv$ ./make.py --board=arty --build17:54
pdp7I created symlink17:55
pdp7 /opt/Xilinx -> /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx17:55
_florent_are you using litex-buildenv or litex directly?17:57
_florent_before building, can you just do "source /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/VIvado2017.3/settings64.sh"?17:58
_florent_sorry "source /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/VIvado/2017.3/settings64.sh"17:58
pdp7ah, let try18:01
pdp7ok,18:02
pdp7pdp7@x1:~/dev/enjoy/linux-on-litex-vexriscv$ source /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/Vivado/2017.3/settings64.sh18:02
pdp7pdp7@x1:~/dev/enjoy/linux-on-litex-vexriscv$ ./make.py --board=arty --build18:02
pdp7but bit different error this time18:02
pdp7source top.tcl18:02
pdp7# create_project -force -name top -part xc7a35ticsg324-1L18:02
pdp7ERROR: [Common 17-685] Unable to load Tcl app xilinx::xsim18:02
pdp7ERROR: [Common 17-69] Command failed: ERROR: [Common 17-685] Unable to load Tcl app xilinx::xsim18:02
pdp7INFO: [Common 17-206] Exiting Vivado at Wed Feb 19 19:00:55 2020...18:02
pdp7running again18:03
pdp7i now get:18:04
pdp7/home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/Vivado/2017.3/bin/rdiArgs.sh: line 179: 30863 Segmentation fault      (core dumped) "$RDI_PROG" "$@"18:04
CarlFKpdp7: what distro/release ?18:05
pdp7that line is:18:05
pdp7  "$RDI_PROG" "$@"18:05
pdp7which turns out to be:18:06
pdp7/home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/vivado18:06
pdp7let me chec18:06
pdp7pdp7@x1:~/dev/enjoy/linux-on-litex-vexriscv$ ldd /home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/vivado18:06
pdp7linux-vdso.so.1 (0x00007ffef2525000)18:06
pdp7libtcmalloc.so.4 => not found18:06
pdp7libboost_signals.so => not found18:06
pdp7librdi_common.so => not found18:06
pdp7librdi_commonmain.so => not found18:06
pdp7libstdc++.so.6 => /lib/x86_64-linux-gnu/libstdc++.so.6 (0x00007f7edd7ff000)18:06
pdp7libgcc_s.so.1 => /lib/x86_64-linux-gnu/libgcc_s.so.1 (0x00007f7edd7e5000)18:06
pdp7libc.so.6 => /lib/x86_64-linux-gnu/libc.so.6 (0x00007f7edd5f2000)18:06
pdp7libm.so.6 => /lib/x86_64-linux-gnu/libm.so.6 (0x00007f7edd4a3000)18:06
pdp7/lib64/ld-linux-x86-64.so.2 (0x00007f7edda0e000)18:06
pdp7could be problem18:06
pdp7@CarlFK Ubuntu 19.1018:07
pdp7with Vivado 2017.318:07
pdp7_florent_:  are there instructions with regard to linux-on-litex-vexriscv and vivado ?18:08
_florent_the issue seems to be related to the Vivado version/Ubuntu version18:10
CarlFKpdp7: your vivado seems to be 'broken' (or crashing...)  give me 20 min and I'll try to set up the same thing here18:10
pdp7yeah, installing some packages18:10
pdp7also18:12
pdp7export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.3/lib/lnx64.o:$LD_LIBRARY_PATH18:12
pdp7hmmm18:13
pdp7ldd is happy now18:14
pdp7but18:14
pdp7$ /opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/vivado18:14
pdp7Error: The file  is corrupt. Please re-install this software from the original media.18:14
pdp7Aborted (core dumped)18:14
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pdp7pdp7@x1:~/dev/enjoy/linux-on-litex-vexriscv$ /opt/Xilinx/Vivado/2017.3/bin/vivado18:15
pdp7DEBUG:RDI_PROG:/opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/vivado18:15
pdp7****** Vivado v2017.3 (64-bit)18:15
pdp7  **** SW Build 2018833 on Wed Oct  4 19:58:07 MDT 201718:15
pdp7  **** IP Build 2016188 on Wed Oct  4 21:52:56 MDT 201718:15
pdp7    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.18:15
pdp7start_gui18:15
pdp7ERROR: [Common 17-267] Couldn't open 'libjvm.so': 'libjvm.so: cannot open shared object file: No such file or directory'18:15
pdp7Make sure you are using a supported OS of RHEL5.x or greater.18:15
pdp7ERROR: [Common 17-211] Error loading jvm.18:15
pdp7Vivado%18:15
_florent_if you have space (and time...) you should probably update your Vivado version to 2019.218:15
pdp7ok18:15
pdp7 Xilinx Unified Installer Update 1 - 2019.2 (TAR/GZIP - 9.03 GB)18:16
pdp7sound right?18:16
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pdp7time to clean my hard drive18:20
pdp7mithro: is symbiflow ready yet? :)18:20
CarlFKpdp7: 22964656463   Xilinx_Vivado_SDK_2019.1_0524_1430.tar.gz18:20
pdp7thanks18:21
CarlFKhmm, 2019.2... looks more current than what I have...18:21
pdp7i'm downloading Xilinx_Vivado_Vitis_Update_2019.2.1_1205_0436.tar.gz18:21
CarlFKyeah, now I am too :p18:21
pdp713 minutes left18:21
mithropdp7: Had the first success with DDR on the Arty yesterday18:23
pdp7awesome!18:24
_florent_mithro: great!18:49
pdp7CarlFK: trying to install Xilinx_Vivado_Vitis_Update_2019.2.1_1205_0436 now19:16
CarlFKpdp7: im confused... https://www.xilinx.com/support/download.html  says "Vivado Design Suite 2019.2.1 is now available..."19:17
tpbTitle: Downloads (at www.xilinx.com)19:17
CarlFKbut I don't see 2019.2.1... where did you find it?19:18
pdp7 Xilinx Unified Installer Update 1 - 2019.2 (TAR/GZIP - 9.03 GB)19:18
pdp7under Vivado Design Suite - HLx Editions Update 1 - 2019.219:18
CarlFKgot it.  thanks.19:18
pdp7ugh... "there is no valid Xilinx installation that this update can be applied to"19:20
pdp7CarlFK: ok, now I downloaded Xilinx_Unified_2019.2_1106_2127_Lin64.bin19:23
pdp7https://xilinx-ax-dl.entitlenow.com/dl/ul/2019/11/08/R210260636/Xilinx_Unified_2019.2_1106_2127_Lin64.bin/73f8ee01875047cfb5de619c1400401e/5E4DDE9F?akdm=0&filename=Xilinx_Unified_2019.2_1106_2127_Lin64.bin19:23
pdp7ugh, it's a java program install wizard19:24
pdp7hmm I have to choose between Vitis and Vivado19:25
pdp7in radio button dialog19:25
pdp7oh god, requires 46 GB19:27
somlo_florent_: Thanks again for the litesdcard clocker fix, now https://hastebin.com/uleyeyilow.rb works with Rocket at 60MHz (and also with vexriscv at 100MHz and below)19:27
CarlFKpdp7: yeah, yuck.  you can install to a thumb drive and then make a sym link19:31
CarlFKim trying to clear out space for the download before my disk fills up...19:32
CarlFKrm ubuntu-19.10-desktop-amd64.iso  4G feed up.. not eneough...19:33
pdp7wow, this is crazy... now i know why yosys and nextpnr is so nice19:34
CarlFKgeeze.. 3 hours of dl left.. 3.5 of 26 gig!!!19:48
pdp7yikes19:51
pdp7i'm going back trying to fix /opt/Xilinx/Vivado/2017.3/19:51
pdp7stuck on19:55
pdp7pdp7@x1:/opt/Xilinx/Vivado/2017.3$ vivado19:55
pdp7DEBUG:RDI_PROG:/home/pdp7/dev/litex-buildenv/build/Xilinx/opt/Xilinx/Vivado/2017.3/bin/unwrapped/lnx64.o/vivado19:55
pdp7****** Vivado v2017.3 (64-bit)19:55
pdp7  **** SW Build 2018833 on Wed Oct  4 19:58:07 MDT 201719:55
pdp7  **** IP Build 2016188 on Wed Oct  4 21:52:56 MDT 201719:55
pdp7    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.19:55
pdp7start_gui19:55
pdp7ERROR: [Common 17-70] Application Exception: JVM classPath has not yet been set19:55
pdp7ERROR: [Common 17-211] Error loading jvm.19:55
pdp7Vivado% exit19:55
somlodaveshah: random data point on trellisboard -- I noticed that generally correct and working Litex+Rocket bitstreams will pass memtest almost 100% of the time after the board has been plugged in and powered for "a while" (hours); however, after it's been unplugged for a while, it tends to fail memtest using the same exact bitstream20:02
somloso once it "warms up" it seems the DRAM circuitry tends to work better (and I literally mean I think temperature has something to do with it :) )20:03
daveshahSeems quite plausible20:03
daveshahI think 55-60MHz is the low end of what the internal delay loop thingy supports20:03
daveshahstuff tends to get slower as it warms up20:03
somloI run it at 60MHz because I tend to be intimidated a bit by nextpnr "failing" to guarantee the requested fmax :)20:04
somloI could probably try 65MHz, but then if I start seeing random glitches while in linux I fear I'll have trouble blaming the appropriate layer...20:05
daveshahYeah, there's no way around it with rocket, unless you somehow ran litedram at a higher clock20:05
somlobut anyway, I'm happy to hear the temperature thing makes sense -- thanks!20:07
sorearmight be interesting to experiment with a controlled temperature?  maybe have it off for a while, but in an 80C oven20:07
pdp7python3 -m litex.soc.software.mkmscimg bios.bin --little20:08
pdp7****** Vivado v2017.3 (64-bit)20:08
pdp7  **** SW Build 2018833 on Wed Oct  4 19:58:07 MDT 201720:08
pdp7  **** IP Build 2016188 on Wed Oct  4 21:52:56 MDT 201720:08
pdp7    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.20:08
pdp7source top.tcl20:08
pdp7# create_project -force -name top -part xc7a35ticsg324-1L20:08
pdp7ERROR: [Common 17-685] Unable to load Tcl app xilinx::xsim20:09
pdp7ERROR: [Common 17-69] Command failed: ERROR: [Common 17-685] Unable to load Tcl app xilinx::xsim20:09
pdp7INFO: [Common 17-206] Exiting Vivado at Wed Feb 19 21:03:40 2020...20:09
somlosorear: that'd be interesting indeed, but I'm not set up to do that test (I'm really just a software guy trying to fake it :D )20:09
pdp7ugh, tcl and big binaries...20:09
pdp7daveshah: can I use nextpnr for arty (artix7)? :)20:09
daveshahYou can but it's pretty finnicky at the moment20:09
pdp7seems better than finding 40GB of space :)20:10
daveshah(https://github.com/daveshah1/nextpnr-xilinx/)20:10
tpbTitle: GitHub - daveshah1/nextpnr-xilinx: Experimental flows using nextpnr for Xilinx devices (at github.com)20:10
pdp7nice, there is Arty example in the readme.  thanks20:11
daveshahYou can disable devices in Vivado to reduce the space it needs btw20:11
pdp7looks like the smallest I can acheive is 40GB20:19
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pdp7mithro: any idea why this is failing?22:23
pdp7https://www.irccloud.com/pastebin/GbYIWKDp/22:23
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)22:23
pdp7from https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode#boot-linux-via-tftp22:23
tpbTitle: HowTo LCA2018 FPGA Miniconf VexRiscv Renode · timvideos/litex-buildenv Wiki · GitHub (at github.com)22:23
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