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| pdp7 | _florent_: hi, re: booting from flash on github, I'm also in irc. thanks for looking at the arty | 12:08 |
|---|---|---|
| pdp7 | -Drew | 12:08 |
| somlo | I tried to build a LiteX SoC with *both* ethernet and SDcard: https://pastebin.com/tQD7ZUDd on a nexys4ddr, with vivado, and it keeps failing to meet timing constraints (even at Fmax as low as 10MHz) | 12:15 |
| tpb | Title: [Diff] diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr. - Pastebin.com (at pastebin.com) | 12:15 |
| somlo | either one by itself is ok at 50-75 MHz... | 12:16 |
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| _florent_ | pdp7: i just got booting from flash working on Arty, i'll update the github issue | 18:49 |
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| daveshah | Does anyone else have a Genesys2 board? I can't get Ethernet to work with LiteX, it sends ARPs but appears not to receive anything (I'll keep debugging but just putting it out there) | 19:03 |
| daveshah | hmm, this is odd, seems like this param goes missing somewhere https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/s7rgmii.py#L106 | 19:14 |
| tpb | Title: liteeth/s7rgmii.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 19:14 |
| daveshah | oh never mind, my python setup was in a mess and a different liteeth was being used | 19:18 |
| daveshah | working fine now, sorry for the noise | 19:22 |
| Finde | daveshah: if you ever need other help we have about 20 and would be happy to try things out for you | 19:24 |
| daveshah | Cool, thanks! | 19:24 |
| Finde | we == OpenPiton team btw | 19:25 |
| Finde | _florent_: Fei managed to run his ComputeDRAM on LiteDRAM/LiteX the other day on VC707 :) | 19:25 |
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| somlo | hmm... I misspoke earlier; looks like I can't get 40MHz on the nexys4ddr even if I leave out the Ethernet hardware (s/EthernetSoC/BaseSoC/ in line 26 of https://pastebin.com/tQD7ZUDd ) | 19:59 |
| tpb | Title: [Diff] diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr. - Pastebin.com (at pastebin.com) | 19:59 |
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| daveshah | somlo: what is the exact timing issue that is reported? | 20:10 |
| somlo | daveshah: http://mirror.ini.cmu.edu/top_timing.rpt (asked for --sys-clk-freq 30e6) | 20:21 |
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| daveshah | somlo: looks like something is wrong with the MMCM? | 20:24 |
| daveshah | the main clock domain looks fine, it seems to be something odd with the mmcm clock signals | 20:25 |
| somlo | yeah, and it only happens when I try to connect litesdcard | 20:28 |
| somlo | I remember this stuf working about 3-4 weeks ago, so maybe I should just bisect LiteX (litesdcard didn't change significantly since then) | 20:29 |
| somlo | maybe all those "add_period_constraints" statements I cribbed from litesdcard/examples/nexys4ddr.py are now wrong, post new_soc... | 20:32 |
| daveshah | I suspect the problem will be around this MMCM https://github.com/lambdaconcept/litesdcard/blob/master/litesdcard/clocker.py#L113 | 20:33 |
| tpb | Title: litesdcard/clocker.py at master · lambdaconcept/litesdcard · GitHub (at github.com) | 20:33 |
| somlo | daveshah: thanks, I'll stare at it until it hopefully starts making sense :) It's timely, too, since I'll need to figure out a way to "port" the xilinx-isms over to the trellisboard to try and use its own sdcard slot :) | 20:38 |
| _florent_ | Finde: nice for ComputeDRAM, i'll have a closer look at it | 20:49 |
| _florent_ | daveshah: i also have a genesys2 if needed | 20:49 |
| _florent_ | somlo: i could look at your nexys4ddr design tomorrow | 20:49 |
| somlo | _florent_: thanks! | 20:54 |
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| somlo | _florent_: also, orthogonal to litesdcard: litex commit 0497f3ca results in a trellisboard bitstream that completely fails to initialize the SoC upon download via openocd | 22:52 |
| somlo | haven't tried it on nexys4ddr (and can't try it on ecp5versa, at least not with rocket) | 22:53 |
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