Saturday, 2019-12-28

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xobsA bit of a historical question: Does anyone know why the litex vexriscv doesn't use standard CSR numbers for things like MIP and MIE? https://github.com/enjoy-digital/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenCoreDefault.scala#L20809:54
tpbTitle: VexRiscv-verilog/GenCoreDefault.scala at master · enjoy-digital/VexRiscv-verilog · GitHub (at github.com)09:54
daveshahAt least historically I don't think it was compliant as it wasn't a standard PLIC09:56
xobsHmm...  I guess the real question I have is: Should I change it back in my designs (i.e. is it compliant now)?09:57
xobsI'm working on Rust support, and I have a forked version of `riscv` that adds `vmim`, `vmip`, `vdci`, `vsim`, and `vsip` calls.09:58
daveshahI haven't followed VexRiscv enough to know10:00
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rvense_florent_: i'm havingg trouble getting a working cpu with litex-buildenv for my lattice hx8k evb. the cpu and wishbon bus just lock up. i've been with tim and xobs for a few hours at ccc, and they think it's related to a change you made with how memory regions are set up.17:48
_florent_rvense: can you share the target file of give a link to it?19:14
rvensei just followed https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards19:20
tpbTitle: HowTo FuPy on iCE40 Boards · timvideos/litex-buildenv Wiki · GitHub (at github.com)19:20
rvenseso https://github.com/timvideos/litex-buildenv/blob/master/targets/ice40_hx8k_b_evn/base.py19:20
tpbTitle: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com)19:20
mithro_florent_: we have discovered that it is happening because nothing is mapped to address 019:21
rvensecommit 96ab220b0f60e3d509ca0a66dcfb81676ef294d9 produced a working image19:22
_florent_mithro, rvense: ok, i'll look at that20:22
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futarisIRCcloudhttps://twitter.com/pdp7/status/1210885427336495104?s=1923:46
futarisIRCcloudQwertyEmbedded: All I had to do was sleep.23:47

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