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| acathla | _florent_, it works! Thank you | 15:31 |
|---|---|---|
| acathla | Now, I can write to the uart, read the first char available on rxtx, but not the following chars... | 15:34 |
| acathla | oh, just found it, a bit by chance. | 15:37 |
| _florent_ | acathla: ok so you are doing that in simulation? | 15:57 |
| acathla | I'm testing an uart on the wishbone bus through an UART-wishbone bridge. The goal is to test a modified uart to do infrared communication | 16:03 |
| somlo | _florent_: https://github.com/litex-hub/linux-on-litex-vexriscv/pull/60 | 16:18 |
| tpb | Title: RFC: update liteeth driver to automatically calculate hwreg offsets by gsomlo · Pull Request #60 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 16:18 |
| somlo | _florent_: it seems csr subregisters show up in native CPU endianness when dumped with the `mr` command from the bios prompt | 16:19 |
| somlo | which is great when writing software, not complaining, but a bit unexpected -- I thought they'd be stored the same way regardless of the CPU endianness. Am I missing something? | 16:20 |
| _florent_ | acathla: ok good | 16:29 |
| _florent_ | somlo: thanks for the investigation, i need to look at the code to answer, i'll try to do that later today | 16:30 |
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