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| _florent_ | somlo: are you sure it's worth having an AXI ports with data_width > 64-bit on rocket? If you want to do some test with 64-bit AXI with the trellis board, you can also change the platform file and only keep 1 dm, 8 dq, 1 dqs. It will also divide the memory size by 4, but should allow you to evaluate the performance until we have AXI converters. | 08:58 |
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| somlo | daveshah: ^^ | 14:30 |
| somlo | daveshah: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/partner/platforms/trellisboard.py#L66 | 14:30 |
| tpb | Title: litex-boards/trellisboard.py at master · litex-hub/litex-boards · GitHub (at github.com) | 14:30 |
| somlo | I kept R26 for dm, the first row of dq, and R29 for dqs_p | 14:30 |
| somlo | but now nextpnr fails with "terminate called after throwing an instance of 'std::out_of_range'" | 14:31 |
| somlo | "what(): _Map_base::at" | 14:31 |
| somlo | "Aborted (core dumped)" | 14:31 |
| somlo | so I'm probably butchering the platform file in some way that currently escapes me :) | 14:31 |
| somlo | daveshah: yosys git #f02623a, nextpnr git #b582ba8, so not sure they're old enough to qualify for one of the known issues, e.g. https://github.com/YosysHQ/nextpnr/issues/310 | 14:51 |
| tpb | Title: nextpnr-ecp5 throws std::out_of_range when using TRELLIS_SLICE · Issue #310 · YosysHQ/nextpnr · GitHub (at github.com) | 14:51 |
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| daveshah | somlo: nothing to do with your change, it's the ECLKBRIDGE change | 15:41 |
| daveshah | try reverting https://github.com/litex-hub/litex-boards/commit/5bd8c4d74f11ca3c38dd698f46d993d2871b17b4 until I fix nextpnr | 15:41 |
| tpb | Title: targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR… · litex-hub/litex-boards@5bd8c4d · GitHub (at github.com) | 15:41 |
| somlo | daveshah: thanks! | 15:50 |
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| daveshah | somlo: should be fixed upstream now | 16:28 |
| somlo | oh, cool, I'll just give that a spin, then | 17:55 |
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| bonzibuddy | Hey all - i'm having trouble figuring out where I would increase the allocation for ramdisk in the memory space, on the linux-on-litex-vexriscv project | 19:44 |
| bonzibuddy | i feel like images.json has to line up with some other setting elsewhere? | 19:45 |
| bonzibuddy | ah. soc_cles.mem_map looks promising | 19:47 |
| bonzibuddy | + json2dts.py | 19:59 |
| bonzibuddy | if there are other spots where 'changing ramdisk size' would come into play id love to hear it :) | 19:59 |
| bonzibuddy | hum. now linux is not booting | 20:13 |
| _florent_ | bonzibuddy: you can probably increase it by changing initrd-end in the dts: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/json2dts.py#L44 | 20:25 |
| tpb | Title: linux-on-litex-vexriscv/json2dts.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 20:25 |
| bonzibuddy | that's what ive done, but i made it way too big perhaps? so now im catering it to my image size | 20:32 |
| bonzibuddy | _florent_ thanks! | 20:32 |
| bonzibuddy | rebuilding everything now | 20:41 |
| _florent_ | also, make sure to update images.json to reflect the initrd-end increase: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/images.json#L3-L4 | 21:08 |
| tpb | Title: linux-on-litex-vexriscv/images.json at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 21:08 |
| bonzibuddy | gotcha. yep, have done those two things | 21:16 |
| bonzibuddy | test is uploading now | 21:16 |
| bonzibuddy | it still gets stuck at 'Booting Linux' :. | 21:20 |
| bonzibuddy | derp. think i got the offset wrong on the initrd-end in json2dts | 21:24 |
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| bonzibuddy | still no luck :/ ill get a pastebin going | 21:39 |
| bonzibuddy | https://pastebin.com/hs6hLTVc | 21:47 |
| bonzibuddy | i think i mucked up my rootfs build so im redoing that one now | 21:47 |
| bonzibuddy | ugh it keeps getting stuck at booting linux :( | 22:24 |
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