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| scanakci | I have a question related to testing strategy that we should have for integrating a cpu in litex. We figured out how blackparrot off-chip link interface looks like and currently writing a convertor to adapt the BB memory interface to wishbone(BP2WB). Soon, we would like to test Blackparrot&BP2WB convertor and see if communication between BlackParrot core and Litex DRAM goes correct. Blackparrot repo has some basic | 02:55 |
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| scanakci | helloworld testbenchs, so I was planning to use one of those as a first step in Litex. Is this straightforward? litex_sim seems to run BIOS for current CPUs and I think it is a bit aggressive test for first shot. Any feedback, suggestion will be so helpful. | 02:55 |
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| forksand | Where is the best place to set the ethernet MAC address to a static address (instead of a random MAC each time fpga is programmed)? | 17:25 |
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| _florent_ | somlo: i'll try to see if i can add an AXI converter in the next weeks (this will also be useful for the others CPUs using AXI) | 21:04 |
| _florent_ | scanakci: for the first tests, you can | 21:06 |
| _florent_ | you can use litex-sim with --rom-init to use you software instead of the BIOS | 21:08 |
| _florent_ | you can also trace the signals by adding --trace | 21:09 |
| _florent_ | once you have the bios working and want to test with LiteDRAM in simulation, use --with-sdram and it will use a SDRAM instead of the integrated main_ram | 21:10 |
| _florent_ | forksand: the mac address is specified here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/boot.c#L238 | 21:19 |
| tpb | Title: litex/boot.c at master · enjoy-digital/litex · GitHub (at github.com) | 21:19 |
| _florent_ | it's static for now, but we could make it configurable and loaded from an EEPROM or SPI Flash | 21:19 |
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| somlo | _florent_: looks pretty straightforward to specify the mem_axi data_width on the rocket verilog side (even independently of the mmio_axi data_width!) | 22:00 |
| somlo | but rather than a cpu-type x mem_axi_datawidth matrix of pre-generated verilog, it'll be nice to have a rocket with mem_axi datawidth set to the widest LiteDRAM configuration (128bit on the versa, gotta find out about trellis), and down-convert for boards where it is narrower | 22:01 |
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| futarisIRCcloud | John_K / mithro / _florent_ : Looks like DDR2 on Pano Logic just got solved recently. cryozap and ali_as were talking about it on ##fpga. | 23:57 |
| futarisIRCcloud | https://twitter.com/tom_verbeure/status/1186059662648475649 | 23:57 |
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