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| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 00:28 |
| cansu | a | 00:34 |
| cansu | Hi, as @scanakci mentioned, we are trying to integrate Black Parrot CPU into Litex. Black Parrot will use AXI as bus protocol and I just wanted to be sure that my understanding is correct. @gsomlo, In Rocket, you have adapted Wishbone to AXI and there already exists an interface between those two, right? I assume with some minor modifications, we can make the connection between Black parrot and Wishbone without the | 00:35 |
| cansu | need of a new shim. I would appreciate if you can correct me if I am wrong. Thanks in advance! | 00:35 |
| cansu | Sorry for the typo @somlo | 00:38 |
| sorear | how much public information on the plans for black parrot are there | 00:38 |
| scanakci | I and Cansu recently started looking into that. Other than github repo, there are short workshop papers, and presentations about it. | 00:56 |
| scanakci | sorear: https://uploads-ssl.webflow.com/5a749b2fa5fde0000189ffc0/5d7feda4e41cc12b268581d2_22POSH%20Washington%20Taylor%20Website.pdf | 00:57 |
| sorear | are you insiders | 00:57 |
| scanakci | currently, we are not working on hardware development. My labmates were working on it till some point. We collaborate with University of Washington to add LiteX support. | 00:59 |
| sorear | I’m very curious about what your plans are to become compellingly better than Rocket | 01:01 |
| somlo | cansu: start by looking at https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/rocket/core.py and its relationship to the rocket-chip Verilog module it connects to (e.g., freechips.rocketchip.system.LitexLinuxConfig.v) | 01:05 |
| tpb | Title: litex/core.py at master · enjoy-digital/litex · GitHub (at github.com) | 01:05 |
| scanakci | sorear: I really do not have much background neither on Rocket nor Blackparrot to answer that. | 01:06 |
| somlo | right now, Litex's main system bus is 32-bit wishbone, so rocket's core.py adds a 64bit AXI-to-wishbone, and a 64-to-32bit wishbone down-converter to *both* of Rocket's axi interfaces, before connecting them to the wishbone bus as masters | 01:07 |
| somlo | that's a bit suboptimal, as Rocket does its own internal routing: cached ram accesses over a mem-AXI, and MMIO accesses over a second mmio-AXI interface | 01:08 |
| somlo | does Black Parrot's verilog interface provide more than one AXI master interface? | 01:09 |
| somlo | you should start by connecting them all to the LiteX 32-bit wishbone as masters, similarly to how Rocket is doing it right now | 01:10 |
| somlo | In the mean time, I'm trying to find the cycles to connect cached RAM directly to LiteDRAM's data via a dedicated, native-AXI link | 01:10 |
| somlo | leaving just MMIO accesses via the 64-to-32 axi->wishbone downshifter | 01:11 |
| somlo | but you should not need to do that during your first pass, better to keep things simple until you get something working | 01:11 |
| cansu | somlo: Thanks a lot! Black Parrot’s verilog interface is under development. We will probably have a better idea in the next 2 weeks how their AXI will look like. | 01:14 |
| somlo | sorear: w/o being familiar with Black Parrot (or Ariane, for that matter), I like the idea of something written natively in Verilog, whether it beats rocket in performance or not :) | 01:14 |
| sorear | hmm, if there are (a) BU people (b) with significant technical and planning knoledge of BlackParrot around I’d like to get to know them | 01:14 |
| sorear | somlo: depressing but valid, rip vscale | 01:15 |
| scanakci | somlo: Thank you so much. I have a separate question than this. Did you simulate Linux on Rocket Core using Litex? I read your blog about FPGA implementation but could not see something similar to linux-on-vexriscv Litex repo. | 01:16 |
| scanakci | I can simulate BIOS using litex_sim using any of the variants. I was curious if went further than BIOS on simulation | 01:17 |
| somlo | scanakci: I used the litex built-in (verilator-based) simulator to get rocket all the way into loading the bios | 01:18 |
| somlo | litex/litex/tools/litex_sim.py --with-ethernet --with-sdram --cpu-type rocket --cpu-variant linux | 01:19 |
| somlo | I did try to load linux from there (had to pre-load the memory with --ram-init something.bin, waiting for verilator to simulate the ethernet interface was too slow) | 01:21 |
| scanakci | I see. Do you think that it is better for me to switch to FPGA after coming to this point(loading the bios) or booting up the linux in the same simulation environment? | 01:21 |
| somlo | and it takes a looong time to actually boot linux on a 64-bit simulated chip, but you do get to see it happen | 01:21 |
| scanakci | I see, thank you. I will probably go on with FPGA once we come to the loading the bios point | 01:22 |
| somlo | I'd go as far as making sure I'm seeing the kernel print out things to the console, or at least get the simulator to prove you're executing early boot code, before switching to an fpga | 01:22 |
| scanakci | Sure. Currently, where do you store the BIOS in Litex environment? | 01:23 |
| scanakci | is it in SRAM since you launch the simulator wiith that option? | 01:24 |
| somlo | I think the bios is always in SRAM, whether simulated or part of an fpga bitstream image | 01:25 |
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| acathla | Ok, I'm lost. What's the best practice with litex? Where do I put my own code, how does it (python) finds it? How compatible an example from litex-buildenv can be with standalone litex? | 08:22 |
| acathla | I copied a tinyfpga_bx/base.py to litex/litex/boards/targets but it's still using litex from litex-buildenv/third_party/... | 08:27 |
| _florent_ | acathla: i can explain you how to do things with standalone litex | 08:53 |
| _florent_ | install migen, litex, the core with litex_setup.py: | 08:54 |
| acathla | I found (again) the sys.path changed, a clean shell helps | 08:54 |
| _florent_ | wget https://github.com/enjoy-digital/litex/blob/master/litex_setup.py | 08:54 |
| tpb | Title: litex/litex_setup.py at master · enjoy-digital/litex · GitHub (at github.com) | 08:54 |
| _florent_ | then python3 litex_setup.py init install | 08:54 |
| acathla | Did that yesterday, it's ok | 08:54 |
| _florent_ | ok | 08:55 |
| acathla | Well, I hope | 08:55 |
| _florent_ | so then if you want to create your board design, let's say based on one of the available target in https://github.com/enjoy-digital/litex/tree/master/litex/boards/targets | 08:55 |
| tpb | Title: litex/litex/boards/targets at master · enjoy-digital/litex · GitHub (at github.com) | 08:55 |
| _florent_ | you can just copy it in your project, customize it and just execute it | 08:56 |
| _florent_ | when doing that, is it still using litex-buildenv/third_party/? | 08:57 |
| acathla | I closed the terminal and it's OK now | 08:58 |
| acathla | Well I have a "NameError: name 'AXIInterface' is not defined" now | 08:59 |
| _florent_ | hmm strange, can you give the full message error? | 09:11 |
| acathla | Traceback (most recent call last): | 09:12 |
| acathla | File "simple.py", line 13, in <module> | 09:12 |
| acathla | from litex.soc.integration.soc_core import * | 09:12 |
| acathla | File "/usr/local/lib/python3.6/dist-packages/litex-0.2.dev0-py3.6.egg/litex/soc/integration/__init__.py", line 2, in <module> | 09:12 |
| acathla | from litex.soc.integration.soc_sdram import SoCSDRAM | 09:12 |
| acathla | File "/usr/local/lib/python3.6/dist-packages/litex-0.2.dev0-py3.6.egg/litex/soc/integration/soc_sdram.py", line 9, in <module> | 09:12 |
| acathla | from litedram.frontend.axi import * | 09:12 |
| acathla | File "/home/fabien/prog/litex/litedram/litedram/frontend/axi.py", line 28, in <module> | 09:12 |
| acathla | class LiteDRAMAXIPort(AXIInterface): | 09:12 |
| acathla | NameError: name 'AXIInterface' is not defined | 09:12 |
| acathla | Even when doing "python3 simple.py" | 09:12 |
| _florent_ | AXI interface should be imported with from litex.soc.interconnect.axi import * | 09:15 |
| _florent_ | can you check your /usr/local/lib/python3.6/dist-packages/litex-0.2.dev0-py3.6.egg/litex/soc/interconnect/axi.py? | 09:16 |
| _florent_ | for info, here is how Travis is doing install, running the tests: https://github.com/enjoy-digital/litex/blob/master/.travis.yml | 09:19 |
| tpb | Title: litex/.travis.yml at master · enjoy-digital/litex · GitHub (at github.com) | 09:19 |
| _florent_ | and it's executing test_targets: https://github.com/enjoy-digital/litex/blob/master/test/test_targets.py | 09:19 |
| tpb | Title: litex/test_targets.py at master · enjoy-digital/litex · GitHub (at github.com) | 09:19 |
| _florent_ | so i think you have a conflict somewhere between versions | 09:20 |
| acathla | I removed everything in /usr/local/lib/python3.6/dist-packages/*, I had different versions of migen and... dust | 09:24 |
| acathla | now I have egg-links, and : File "simple.py", line 13, in <module> | 09:24 |
| acathla | from litex.soc.integration.soc_core import * | 09:24 |
| acathla | ModuleNotFoundError: No module named 'litex' | 09:24 |
| acathla | " | 09:24 |
| _florent_ | you just removed everything and executed litex_setup.py init install? | 09:28 |
| _florent_ | maybe add a sudo before python3 litex_setup.pu init install | 09:29 |
| acathla | I did. I had to do a sudo python3 setup.py install to add litex | 09:30 |
| acathla | And now I still have the AXI problem :( | 09:31 |
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| acathla | Ok, rm -Rfing everything... | 09:41 |
| _florent_ | yes that's probably better, then use litex_setup.py script | 09:43 |
| acathla | Ok, I had old litex stuff probably installed by hand (git clone) a long time ago | 09:51 |
| acathla | Everything seems to be in place. So now, where's the best place to put my migen libs ? in litex-buildenv there is a gateware directory, should I use the "gen" directory? | 09:58 |
| acathla | there should be a library directory, arduino like (sorry), to easily add third party libs or your own | 10:00 |
| _florent_ | in fact, now that it's installed, you just can execute the target in place, so you are free to choose how you want to organize things :) | 10:12 |
| _florent_ | for example: create your own library with a setup.py | 10:13 |
| _florent_ | or for simple project, just have your custom library files near your target | 10:13 |
| _florent_ | or put that in a gateware directory as done in litex-buildenv | 10:13 |
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| acathla | _florent_, thank you, I progress. Now the vexriscv-lite does not want to be built by yosys :( | 15:07 |
| _florent_ | ah, what's the issue? which board are you using? | 15:08 |
| acathla | tinyfpga_bx | 15:11 |
| acathla | old, but not too old, version of yosys works | 15:11 |
| _florent_ | ok, the tinyfpga_bx does not have that much block ram memory, so it's possible you'll have to reduce ROM/SRAM sizes | 15:15 |
| acathla | Yosys from github says : "ERROR: multiple drivers on net 'CO' (carry.CO and $logic_or$/usr/local/bin/../share/yosys/ice40/cells_sim.v:145$1491.Y)" | 15:21 |
| acathla | (version Yosys 0.9+899 ) | 15:22 |
| daveshah | You might need newer nextpnr | 15:24 |
| daveshah | There have been changes to the JSON format | 15:24 |
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| _florent_ | acathla:if needed you can find prebuilt toolchain here: https://github.com/im-tomu/fomu-toolchain/releases | 15:59 |
| tpb | Title: Releases · im-tomu/fomu-toolchain · GitHub (at github.com) | 15:59 |
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| acathla | _florent_, it's ok, after a crash because linux cannot handle correctly the lack of memory, everything seems to be built | 16:06 |
| acathla | LED is still not blinking but, gateware/firmware were built | 16:13 |
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| _florent_ | acathla: good | 16:56 |
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| somlo | \o/ -- my batch of TrellisBoards (https://github.com/daveshah1/TrellisBoard) just got delivered! As soon as I find a set of rubber "feet", it's off to getting litex+rocket running on an 85k ecp5 :) | 18:06 |
| tpb | Title: GitHub - daveshah1/TrellisBoard: Ultimate ECP5 development board (at github.com) | 18:06 |
| somlo | daveshah: I'm assuming the power supply from the versa should work, not sure about what usb cable I should use for programming and serial console | 18:07 |
| daveshah | Make sure you put a jumper on the USB setting of J15, connect type C (start with type C not 12V) | 18:07 |
| somlo | hmm, add "type-c usb cable" to the list of things I need to procure before I can start having some fun... :) | 18:08 |
| daveshah | This is a simple demo: https://github.com/daveshah1/TrellisBoard/tree/master/gateware/simple | 18:09 |
| tpb | Title: TrellisBoard/gateware/simple at master · daveshah1/TrellisBoard · GitHub (at github.com) | 18:09 |
| daveshah | Any irl phone or tech shop should sell them | 18:09 |
| CarlFK | anyone with a printer should have one | 18:11 |
| daveshah | That's type B not C | 18:16 |
| daveshah | Although a lot of phones etc these days are C | 18:16 |
| CarlFK | oh right, never mind | 18:16 |
| somlo | a bunch of my coworkers have newer mac laptops with usb-c, but all I saw was c-to-c cables or those c-to-(a,dvi,power) dongles | 18:17 |
| somlo | I need an honest to goodnes A-to-C cable, gotta go shopping :) | 18:18 |
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| forksand | somlo: i have some notes & issues forming here and am going to set up a wiki about the Trellisboard i had built, fyi: | 18:45 |
| forksand | https://code.forksand.com/forksand/fs-TrellisBoard/ | 18:45 |
| forksand | If you have any easy questions let me know. daveshah will have to answer the hard ones. :) | 18:45 |
| tpb | Title: forksand/fs-TrellisBoard: Ultimate ECP5 Board. Fork Sand fork of https://github.com/daveshah1/TrellisBoard - fs-TrellisBoard - Fork Sand Source Code (at code.forksand.com) | 18:45 |
| somlo | forksand: thanks, will check it out! | 18:53 |
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| somlo | daveshah: re. yosys PR 1425 & nextpnr PR 337, on the ecp5versa and litex+rocket | 20:08 |
| somlo | with yosys #c7f1368 and nextpnr #927077e I would usually get it to pass 60MHz in about 4-5 attempts (got above 55 on average), with "-abc9 -nowidelut" and the xc7dsp yosys patch applied on top of #c7f1368 | 20:08 |
| somlo | yesterday I updated to yosys #da347b9 and nextpnr #cb8d90b, and only managed three runs this morning before I recompiled them both with PRs 1425 and 337, respectively. About the same area (98% TRELLIS_SLICE) as before, around 55MHz Fmax each run. | 20:08 |
| somlo | with both PRs applied, I'm getting about the same results (after two runs so far -- 98% area, 55-56 MHz Fmax) | 20:08 |
| somlo | I'll start my usual loop and see how long until I manage 60MHz, but it's not immediately different at first glance. | 20:08 |
| somlo | Not sure what else changed since (#c7f1368, #927077e) that would have any bearing on my results... | 20:08 |
| daveshah | Thanks for checking! The reduction might be more in number of BRAMs than in amount of logic, although perhaps not an issue for Rocket | 20:11 |
| somlo | I can re-run with vs. without the PRs and look at BRAMs (didn't occur to me to pay attention, since TRELLIS_SLICE is my constraining factor :) | 20:13 |
| somlo | daveshah: so, before the PRs I get 79% DP16KD, after (with) the PRs it goes down to 56% | 20:32 |
| daveshah | Not bad | 20:33 |
| daveshah | Good to see some improvement | 20:33 |
| somlo | 30% (ish) reduction in utilization, that's totally worth writing home about :) | 20:34 |
| somlo | daveshah: oh, and quite hilariously, after I backed out of the PRs to get you the "before" numbers on DP16KD, that run went on to finish with a 62.01MHz Fmax :) | 20:51 |
| somlo | and just to be sure, I booted linux on it to see if it works (it does)... | 20:57 |
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| scanakci | Does Litex provide L2 cache? For instance, is the L2 in this screenshoot provided by LiteX? https://usercontent.irccloud-cdn.com/file/WwB7kuIS/litex%20example | 22:41 |
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| somlo | scanakci: LiteX does indeed provide a default L2 cache when SDRAM is enabled; start grep-ing for "l2_" from here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L27 | 23:51 |
| tpb | Title: litex/soc_sdram.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:51 |
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