*** tpb has joined #litex | 00:00 | |
*** rohitksingh has quit IRC | 00:33 | |
*** freemint has quit IRC | 00:41 | |
*** freemint has joined #litex | 00:42 | |
*** rohitksingh has joined #litex | 00:59 | |
*** CarlFK has quit IRC | 03:05 | |
*** CarlFK has joined #litex | 03:08 | |
*** rohitksingh has quit IRC | 06:33 | |
*** rohitksingh has joined #litex | 06:34 | |
*** rohitksingh has quit IRC | 09:21 | |
*** CarlFK has quit IRC | 10:59 | |
xobs | _florent_: would those Wishbone changes you made affect the ability to use the vexriscv debug bridge? | 12:52 |
---|---|---|
*** CarlFK has joined #litex | 13:34 | |
daveshah | Trying to build latest linux-on-litex-vexriscv for versa and I'm getting some compile issues. I think everything is up to date. | 13:58 |
daveshah | https://www.irccloud.com/pastebin/IWQDlIbY/ | 13:58 |
tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 13:58 |
daveshah | Seems like these are now lowercase in generated/csr.h? | 13:58 |
daveshah | https://www.irccloud.com/pastebin/437aT0Ys/ | 13:58 |
tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 13:58 |
daveshah | After changing the uses of those macros to lowercase, it builds and works fine. But I don't think this is really an intended change | 14:03 |
somlo | daveshah, _florent_: getting the same thing when building rocket (for ecp5versa and nexys4ddr) | 15:32 |
somlo | commit 8be5824e is the "culprit", apparently | 15:45 |
daveshah | somlo: Incidentally, it would be interesting to see if there's any benefit from https://github.com/YosysHQ/yosys/pull/1425 and https://github.com/YosysHQ/nextpnr/pull/337 on Rocket | 15:50 |
tpb | Title: [WIP] ecp5: Add support for mapping 36-bit wide PDP BRAMs by daveshah1 · Pull Request #1425 · YosysHQ/yosys · GitHub (at github.com) | 15:50 |
daveshah | if you have a chance | 15:50 |
somlo | daveshah: oh, so xc7dsp got merged, and these are fixups on top of it... cool! | 15:52 |
daveshah | Yup | 15:52 |
somlo | I'll try them sometime today and report back (got dragged into some unrelated work over the last couple of weeks, gotta catch up with what happened while I wasn't paying attention :) | 15:53 |
somlo | daveshah, _florent_: https://pastebin.com/DVcb0StH (fixup over 8be5824e) | 16:04 |
somlo | I should probably turn this into a proper litex PR | 16:04 |
somlo | https://github.com/enjoy-digital/litex/pull/270 | 16:18 |
tpb | Title: soc/integration: ensure CSR constants are in uppercase by gsomlo · Pull Request #270 · enjoy-digital/litex · GitHub (at github.com) | 16:18 |
* somlo is off doing a complete toolchain update from github: trellis, nextpnr, and yosys | 16:30 | |
xobs | What kinds of pitfalls will I run into if I have a device on Wishbone that's in a different clock domain? And how is arbitration handled? | 16:43 |
*** rohitksingh has joined #litex | 17:41 | |
*** rohitksingh has quit IRC | 18:52 | |
_florent_ | somlo, daveshah: thanks for catching the case issue, it's merged | 19:46 |
_florent_ | xobs: i haven't really touched wishbone the the last days, i was mostly trying to cleanup SoCCore | 19:50 |
*** CarlFK has quit IRC | 20:08 | |
*** rohitksingh has joined #litex | 20:31 | |
*** rohitksingh has quit IRC | 22:25 | |
*** rohitksingh has joined #litex | 22:25 | |
*** forksand has quit IRC | 22:31 | |
*** CarlFK has joined #litex | 22:38 | |
*** forksand has joined #litex | 22:46 | |
*** rohitksingh has quit IRC | 23:21 | |
*** rohitksingh has joined #litex | 23:27 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!