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| John_K | was chatting @mithro on Twitter about adding Pano Logic G2 support to linux-on-litex-vexriscv. Just got JTAG wired up and talking to the S6. Trying to get the "new" ISE working on Linux to generate a blinky bitstream before diving into litex | 03:48 |
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| John_K | is it typical for ./sim.py to take a long time after printing "Booting Linux" to displaying anything from the kernel? | 04:11 |
| John_K | (for linux-on-litex-vexriscv) | 04:11 |
| John_K | (apparently so, took 8min on my little machine here) | 04:18 |
| CarlFK | John_K: both (based on chat a few hours ago: | 04:27 |
| CarlFK | is it normal that it takes minutes to pass -========== Booting Linux =============-- | 04:27 |
| CarlFK | https://logs.timvideos.us/%23litex/%23litex.2019-08-25.log.html#t2019-08-25T22:33:16 | 04:27 |
| _florent_ | John_K, goran-mahovlic_: for linux, we've switched to a LiteX UART driver recently and it with it, first UART message are not printed as soon as before but only when the driver is loaded, so can be few seconds on hardware, but a few minutes on simulation | 04:43 |
| _florent_ | i'd like to see if we can improve that have the benefits of both: first UART message as early as before and use a real UART driver | 04:44 |
| _florent_ | goran-mahovlic_: for Ethernet, if netboot command is not available in the bios, something is probably wrong in the LiteEthPHYRMII integration | 04:45 |
| _florent_ | goran-mahovlic_: by the way, it's now possible to read/write mdio registers to do some verifications on the PHY | 04:46 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/main.c#L345-L349 | 04:47 |
| tpb | Title: litex/main.c at master · enjoy-digital/litex · GitHub (at github.com) | 04:47 |
| _florent_ | if your PHY address is 1 and you want to do a dump of the 32 first registers: mdiod 1 32 | 04:49 |
| _florent_ | goran-mahovlic_: on the nexys4ddr, the LAN8720A RMII PHY does not have a XTAL and we need to generate the clock, that's why we have the Subsignal("ref_clk", Pins("D5")) | 05:14 |
| _florent_ | if you don't have this on your PMOD, it's that there is a 25MHz XTAL on your PMOD board, so you can just ignore this | 05:15 |
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| olofk | Morning | 09:25 |
| olofk | _florent_: Do I need a 100MHz clock for litesdcard or is 25 enough? | 09:26 |
| olofk | Also, is it possible to move the {I,O}DDR and FDPE instantiations out of the core? I would like to keep it tech-agnostic | 10:07 |
| olofk | _florent_: Shouldn't the sd_rst signal be synced? Seems it's coming directly from the locked signal of the mmcme2 | 10:20 |
| olofk | Is the DRP bus of them MMCM unused or did I wire something up incorrectly? Looks like all input wires are tied to 0 | 10:27 |
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| GoranMahovlic | Tnx, after work I will fork and put my setting so you can check what is wrong --- all is really slow on hardware (if boots it take 15-30mins), and network is not generated... | 11:28 |
| GoranMahovlic | Is it possible to boot from SD? | 11:29 |
| GoranMahovlic | I have added SD card module and set pinout | 11:29 |
| GoranMahovlic | And I do not know how complicate is to add HDMI out is there any board that have it already? | 11:29 |
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| olofk | Ahh.. my internet connection is terrible | 12:20 |
| olofk | Is there any documentation on the LiteDRAM native ports? I think I understand how they work from looking at the signal names but I'm not sure if there are any restrictions I should know about | 12:37 |
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| _florent_ | GoranMahovlic: booting from serial should not be that long, IIRC ~5 mins (unless image size exploded with recent changes) | 13:30 |
| _florent_ | GoranMahovlic: it's not yet possible to boot from SD, but we it's planned, same for HDMI | 13:30 |
| GoranMahovlic | tnx, so I will focus then on adding RMII | 13:31 |
| GoranMahovlic | I already have everything prepared, just have some missing lines or something... | 13:32 |
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| somlo | I finally had a chance to actually test the natively built (with yosys/trellis/nextpnr on fedora-riscv64) bitstream for litex+rocket | 13:49 |
| somlo | and it works! http://www.contrib.andrew.cmu.edu/~somlo/BTCP/#sec_4 | 13:50 |
| tpb | Title: A Trustworthy Free/Libre Linux Capable 64bit RISC-V Computer (at www.contrib.andrew.cmu.edu) | 13:50 |
| somlo | still need to run fedora-riscv64 on an actual litex+rocket 64bit linux system instead of just a qemu VM :) | 13:51 |
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| goran-mahovlic_ | I am back home, will fork and push now for ethernet fix | 14:45 |
| goran-mahovlic_ | is this wrong | 14:57 |
| goran-mahovlic_ | Board.__init__(self, ulx3s.BaseSoC, "serial+ethernet") | 14:57 |
| goran-mahovlic_ | I see on Versa it has ethSoc | 14:58 |
| goran-mahovlic_ | versa_ecp5.EthernetSoC | 14:58 |
| goran-mahovlic_ | will try to change that | 14:58 |
| daveshah | If you have added Ethernet to BaseSoC then it wouldn't be needed | 14:58 |
| daveshah | for Versa we have BaseSoC and then EthernetSoC derives from it adding liteeth | 14:59 |
| goran-mahovlic_ | I have added this https://github.com/goran-mahovlic/litex/commit/41c794576f2b8f4f286e927aabf4c973bee76c6d#diff-6dffc3d6d684b0e53ee204c8a8fd2f38 | 15:05 |
| tpb | Title: Adding changes to use Microchip LAN8720 RMII board and SD card · goran-mahovlic/litex@41c7945 · GitHub (at github.com) | 15:05 |
| goran-mahovlic_ | So I have two SoC and I am using Base - I should put then under one SoC | 15:06 |
| goran-mahovlic_ | https://github.com/goran-mahovlic/litex/blob/master/litex/boards/targets/ulx3s.py | 15:07 |
| tpb | Title: litex/ulx3s.py at master · goran-mahovlic/litex · GitHub (at github.com) | 15:07 |
| goran-mahovlic_ | or I should just pass argument and how | 15:09 |
| goran-mahovlic_ | cls = EthernetSoC if args.with_ethernet else BaseSoC | 15:09 |
| goran-mahovlic_ | ok I have braked platform file will fix it now | 15:28 |
| goran-mahovlic_ | still does not generate network files | 15:56 |
| goran-mahovlic_ | https://gist.github.com/goran-mahovlic/d6abf5a6001f2562c963f6a251cda7cc | 15:56 |
| tpb | Title: main.py · GitHub (at gist.github.com) | 15:56 |
| daveshah | https://gist.github.com/goran-mahovlic/d6abf5a6001f2562c963f6a251cda7cc#file-main-py-L145 should be EthernetSoC not BaseSoC | 15:57 |
| tpb | Title: main.py · GitHub (at gist.github.com) | 15:57 |
| goran-mahovlic_ | ok, now I need to find errors :) | 16:07 |
| goran-mahovlic_ | self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth")) | 16:08 |
| goran-mahovlic_ | TypeError: __init__() missing 1 required positional argument: 'pads' | 16:08 |
| goran-mahovlic_ | I did not update yet o git -- it is wrong file I will do it now | 16:09 |
| goran-mahovlic_ | done -- So this is the module I want to add LiteEthPHYRMII | 16:12 |
| goran-mahovlic_ | it has two bit RX and two bit TX as my board | 16:12 |
| goran-mahovlic_ | I just copy pasted from here https://github.com/goran-mahovlic/litex/blob/master/litex/boards/targets/netv2.py | 16:13 |
| tpb | Title: litex/netv2.py at master · goran-mahovlic/litex · GitHub (at github.com) | 16:13 |
| goran-mahovlic_ | but seams that I did not copy all needed | 16:14 |
| goran-mahovlic_ | ok found it, i removed clk -- will add it again | 16:19 |
| _florent_ | goran-mahovlic_: i just improved serialboot, it should be a lot faster now to boot over serial now: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/43 | 16:37 |
| tpb | Title: Loading images over serial is expected to be slow... but not that slow... · Issue #43 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 16:37 |
| goran-mahovlic_ | _florent: Great,tnx! | 16:38 |
| goran-mahovlic_ | Now I see that LiteEthPHYRMII is not for lattice :) | 16:39 |
| goran-mahovlic_ | ERROR: Module `\ODDRXD1' referenced in module `\top' in cell `\ODDRXD1' is not part of the design. | 16:39 |
| goran-mahovlic_ | Or I am wrong? | 16:39 |
| goran-mahovlic_ | I am probably wrong :) -- modules are complaining about eth clock so I just copy pasted pll.create_clkout(self.cd_eth, 50e6) | 16:41 |
| goran-mahovlic_ | and that is probably wrong | 16:41 |
| daveshah | ODDRXD1 looks like an ECP3 primitive | 16:42 |
| daveshah | The ECP5 equivalent is ODDRX1F | 16:42 |
| _florent_ | daveshah: indeed, it's used for DDROutput | 16:45 |
| _florent_ | goran-mahovlic_: you need to do the changes here: https://github.com/enjoy-digital/litex/blob/master/litex/build/lattice/common.py#L30-L35 | 16:46 |
| tpb | Title: litex/common.py at master · enjoy-digital/litex · GitHub (at github.com) | 16:46 |
| _florent_ | and use a ODDRX1F | 16:46 |
| _florent_ | i'll do the proper changes later to support both ECP3 and ECP5 | 16:47 |
| goran-mahovlic_ | ERROR: Module `ODDRX1F' referenced in module `top' in cell `ODDRX1F' does not have a port named 'DB'. | 16:49 |
| goran-mahovlic_ | is it D0 D1 | 16:52 |
| goran-mahovlic_ | like here https://github.com/emard/galaksija/blob/master/proj/lattice/galaksija_ulx3s_hdmi/top/galaksija_ulx3s.vhd#L186 | 16:53 |
| tpb | Title: galaksija/galaksija_ulx3s.vhd at master · emard/galaksija · GitHub (at github.com) | 16:53 |
| goran-mahovlic_ | Or I will burn my computer building it :) It is doing something | 16:53 |
| _florent_ | goran-mahovlic_: you need to replace DA/DB with D0/D1 | 17:02 |
| goran-mahovlic_ | it compiled but my laptop needed cleaning - will see now how it will go. It started to do something ... And I think I did see IP with nmap -- but will recheck | 17:20 |
| goran-mahovlic_ | I see it in wireshark need to fix port | 17:30 |
| goran-mahovlic_ | seams to work! Tnx _florent and Dave! I will upload it -- it can probably be made better I have just copy pasted :) It is a bit slow but that is maybe expected ... It is still downloading I see on wireshark | 17:53 |
| daveshah | With the ECP5 RGMII it usually downloads in less than 10s, and the link isn't the bottleneck so RGMII vs RMII shouldn't be a big difference | 18:03 |
| daveshah | however, dodgy TFTP servers can sometimes cause odd behaviour | 18:03 |
| _florent_ | goran-mahovlic_: cool it's it's alive, it should not be too long (similar to Arty with MII), so as daveshah is saying, maybe it's related to the known TFTP bug (which i haven't investigated yet...) | 18:28 |
| goran-mahovlic_ | I did not have bios.bin in root folder it has failed so now I am trying again | 18:33 |
| goran-mahovlic_ | probably something else is wrong to -- now it is up for 6 minutes, but yes, probably something missing again on TFTP | 18:37 |
| goran-mahovlic_ | Booting from network... | 18:38 |
| goran-mahovlic_ | Local IP : 192.168.1.51 | 18:38 |
| goran-mahovlic_ | Remote IP: 192.168.1.249 | 18:38 |
| goran-mahovlic_ | Fetching from: UDP/69 | 18:38 |
| goran-mahovlic_ | Unable to download Image over TFTP | 18:38 |
| goran-mahovlic_ | Network boot failed | 18:38 |
| goran-mahovlic_ | Unable to download Linux images, falling back to boot.bin | 18:38 |
| goran-mahovlic_ | Unable to download boot.bin over TFTP | 18:38 |
| goran-mahovlic_ | Network boot failed | 18:38 |
| goran-mahovlic_ | No boot medium found | 18:38 |
| goran-mahovlic_ | where boot.bin needs to be? | 18:38 |
| daveshah | That will depend how the TFTP server is configured | 18:41 |
| daveshah | it needs to be in the root folder your tftp server is serving | 18:41 |
| goran-mahovlic_ | First it starts with the image - and it is loading for 7 minutes after block 2146 it requests boot.bin file and failes | 18:42 |
| daveshah | Some people have found dnsmasq more reliable than tftpd (I find tftp-hpa fine) | 18:44 |
| daveshah | Oh wait | 18:44 |
| daveshah | I wonder if this is the 50MHz bug again (TFTP needs 55MHz+ to be reliable on the Versa) | 18:44 |
| daveshah | although that might only affect Gigabit/RGMII | 18:44 |
| daveshah | *55MHz+ system clock | 18:44 |
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| GoranMahovlic | Well I could also do something not right :) Or in LiteX or on TFTP that is bigger possibility :) | 19:08 |
| GoranMahovlic | Will let you know once I tryout TFTP localy and upload all changes | 19:08 |
| _florent_ | GoranMahovlic: it's also possible you don't have all the files on the tftp | 19:13 |
| GoranMahovlic | well yes :) I did put then like you noted in README, but path or something else could be wrong | 19:15 |
| _florent_ | You need to have Image, rootfs.cpio, rv32.dtb and emulator.bin | 19:15 |
| GoranMahovlic | and bios.bin that what I see on failed TFTP request | 19:15 |
| GoranMahovlic | emulator.bin should be is inside emulator folder? | 19:16 |
| GoranMahovlic | all others I have in root | 19:17 |
| _florent_ | you don't need bios.bin, it's just that it's falling back to bios.bin if it's not possible to find the linux binaries | 19:17 |
| _florent_ | yes, emulator.bin is in emulator | 19:17 |
| GoranMahovlic | ok, but I see on wireshark it starts to download Image and after 7 minutes just asks for bios.bin and fails | 19:18 |
| GoranMahovlic | it is asking for packets really slowly | 19:19 |
| GoranMahovlic | I can probably repeat and put capture online | 19:19 |
| GoranMahovlic | but I will first check TFPT | 19:19 |
| _florent_ | yes sure, i can have a look | 19:19 |
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| GoranMahovlic | https://send.firefox.com/download/66d3ea7db93b2589/#NyDmlifiFuXf_RSSZiv93w | 21:17 |
| tpb | Title: Firefox Send (at send.firefox.com) | 21:17 |
| GoranMahovlic | I have checked and locally I can download Image file in second --- but board is downloading it and fails after some time --- did not wait here to fail, but check start and finish time | 21:18 |
| GoranMahovlic | maybe I messed something in this file https://github.com/goran-mahovlic/litex/blob/master/litex/boards/targets/ulx3s.py | 21:19 |
| tpb | Title: litex/ulx3s.py at master · goran-mahovlic/litex · GitHub (at github.com) | 21:20 |
| daveshah | Something interesting to try is to replace Image and rootfs.cpio with small (e.g. 16-byte) dummies (but keep emulator) | 21:20 |
| GoranMahovlic | cool will try | 21:20 |
| daveshah | This won't load Linux, but it will at least see if you can boot the emulator via tftp | 21:20 |
| GoranMahovlic | yup | 21:21 |
| GoranMahovlic | Booting from serial...Press Q or ESC to abort boot completely.sL5DdSMmkekroTimeoutBooting from network...Local IP : 192.168.1.51Remote IP: 192.168.1.251Fetching from: UDP/69Downloaded 1000 bytes from Image over TFTP to 0xc0000000 | 21:23 |
| daveshah | if it works you should see something like VexRiscv Machine Mode software built ... | 21:24 |
| daveshah | seems like something is still not right with the tftp | 21:24 |
| GoranMahovlic | I can see it is downloading | 21:26 |
| GoranMahovlic | I think it is just slow | 21:26 |
| GoranMahovlic | But yes, I think it would already load 1Mb and emulator is just 10K | 21:34 |
| GoranMahovlic | If I did switch TX0 and TX1 would it get IP and work like this? | 21:35 |
| GoranMahovlic | Or if I get ip all pins are OK | 21:36 |
| daveshah | Pretty sure if you get an IP and see the request the wiring is fine | 21:38 |
| daveshah | I guess a more subtle fault (e.g. signal integrity or timing) could mess up reliability and thus tftp. but margins in rmii should be pretty good | 21:38 |
| GoranMahovlic | I could load over serial and check network then | 21:45 |
| GoranMahovlic | I will leave it so it can see what happened in morning | 22:05 |
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| futarisIRCcloud | John_K: I've got a Pano Logic G2 here too. | 23:32 |
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