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| futarisIRCcloud | https://www.notebookcheck.net/Perf-V-An-FPGA-based-RISC-V-developer-board-which-costs-US-79.424795.0.html | 03:48 |
|---|---|---|
| tpb | Title: Perf-V: An FPGA based RISC-V developer board, which costs US$79 - NotebookCheck.net News (at www.notebookcheck.net) | 03:48 |
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| Dolu | Maybe the best would be to have a good "system on module" kit, and some good mother boards to plug it in ? with the freedoom and ease to create new motherboard without unsolderable BGA chip ? | 10:46 |
| Dolu | <futarisIRCcloud> | 10:46 |
| Dolu | Also for the SPI ethernet modules, it work, quite slow XD, 1 Mb/s for the ENC28J60-H, 2Mb/s for the W5500 | 10:49 |
| Dolu | tested with iperf3 | 10:49 |
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| Dolu | looking at the waves, there is a tonne of SPI zigzag between each real payload transfer | 12:17 |
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| daveshah | Has anyone tried the debug VexRiscvs with LiteX Linux? I'm investigating a crash that only occurs after several megabytes of TCP transfer, probably related to the IRQ driver I've hacked in | 16:05 |
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| daveshah | Nevermind, pretty sure this was just the old WFI bug, I forgot to pull new VexRiscv-verilog for a while (timing is better now too :)) | 16:35 |
| somlo | daveshah: funny you should mention that, I'm currently trying to trace rocket's progress through the linux kernel | 16:37 |
| daveshah | It seems to still be crashing | 16:37 |
| daveshah | Ah, sounds like fun | 16:38 |
| somlo | and the best I could come up with was sprinkling "mul zero, a1, a2" opcodes into the kernel source, and having rocket's verilog $fwrite something whenever that opcode is executed :) | 16:38 |
| somlo | so I can tell if I made it that far or not... | 16:38 |
| daveshah | Hehe, I'm just about to add some GPIO writes to the interrupt handling stuff | 16:38 |
| somlo | still not sure if it's going into an infinite loop, or if simulating a 64bit rocket is just *that* slow... | 16:40 |
| somlo | IIRC, a bunch of the early-boot printk's get buffered somewhere, then plastered to the console once it is initialized; either I'm using the wrong console driver, or it takes more than 8 hours to get to that point :) | 16:41 |
| daveshah | the previous linux on vexriscv had macros DBG and DBGMSG that directly wrote to the LiteX UART without going through printk infrastructure, printing file&line and an optional message | 16:46 |
| daveshah | was very helpful for the early part of debugging | 16:46 |
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| somlo | I think it's an ecall to the "emulator" for putchar/getchar, same as what the hvc0 console driver ends up using | 16:53 |
| somlo | I was thinking of writing just that sort of macro (to also double-check that the ecall putchar thing even works with BBL on my setup) | 16:55 |
| somlo | but got sucked down the breakpoint bread crumb rabbit hole :) | 16:55 |
| somlo | good to know there already is a macro I can cut'n'paste, though -- thanks for mentioning it! | 16:56 |
| daveshah | https://github.com/antmicro/litex-linux-riscv/blob/master/include/utils/puts.h | 16:56 |
| tpb | Title: litex-linux-riscv/puts.h at master · antmicro/litex-linux-riscv · GitHub (at github.com) | 16:56 |
| somlo | oh, this is even lower level than the ecall mechanism, just MMIO register writes :) | 16:57 |
| daveshah | Yup | 16:58 |
| daveshah | Very helpful | 16:58 |
| daveshah | You can also just sprinkle DBGs around for a crude kind of tracing | 16:58 |
| somlo | the big plus here is that this will work on FPGAs, whereas my hack relies on the simulator | 17:00 |
| daveshah | Yes, I was mostly working on FPGAs with that | 17:04 |
| daveshah | Seems like my VexRiscv issue was the old WFI problem, and I was just failing at git submodules | 17:04 |
| daveshah | Fmax for VexRiscv is now 88MHz on ECP5 with nextpnr which is quite tasty | 17:05 |
| Dolu | daveshah : I'm also in a debug phase of ethernet stuff (SPI). Now it seem all ok. Had issues with driver. but nothing from the VexRiscv side. | 18:09 |
| Dolu | There was issue with threaded interrupts | 18:09 |
| Dolu | Which kind of interrupts are you using ? | 18:09 |
| Dolu | (threaded ONESHOT) | 18:09 |
| daveshah | Not actually sure, tbh | 18:10 |
| daveshah | This is the liteeth driver | 18:10 |
| daveshah | Also took the old Antmicro vexriscv csr IRQ driver and updated the CSR values | 18:10 |
| daveshah | seems stable again now | 18:11 |
| Dolu | I can take a look, where is it ? | 18:11 |
| Dolu | Ahhh now that you updated the VexRiscv it isn't crashing anymore ? (daveshah) | 18:12 |
| daveshah | Yup, all stable | 18:12 |
| Dolu | Great :D | 18:12 |
| daveshah | It was just the WFI bug | 18:12 |
| Dolu | That WFI freeze realy scared me XD | 18:12 |
| Dolu | Catched it via FPGA logic analyser, hopefully that wasn't too complicated | 18:13 |
| daveshah | Haven't pushed this version yet, but if you are curious the liteeth driver is https://github.com/daveshah1/litex-linux-riscv/blob/nfs/drivers/net/ethernet/litex/litex_liteeth.c and the interrupt driver is https://github.com/daveshah1/litex-linux-riscv/blob/nfs/drivers/irqchip/irq-vex.c but with new CSR values | 18:13 |
| tpb | Title: litex-linux-riscv/litex_liteeth.c at nfs · daveshah1/litex-linux-riscv · GitHub (at github.com) | 18:13 |
| daveshah | (that is still the old source tree) | 18:13 |
| Dolu | That 88Mhz fmax is on which speed grade and which VexRiscv config ? | 18:13 |
| daveshah | The standard Linux one, not the Fmax one, on a 5G part | 18:13 |
| Dolu | https://github.com/daveshah1/litex-linux-riscv/blob/nfs/drivers/irqchip/irq-vex.c#L58 This assertion is wrong (as far i understand stuff) | 18:16 |
| tpb | Title: litex-linux-riscv/irq-vex.c at nfs · daveshah1/litex-linux-riscv · GitHub (at github.com) | 18:16 |
| Dolu | It fall apart as soon you have threaded IRQ / ONESHOT | 18:16 |
| daveshah | Interesting | 18:17 |
| Dolu | I just opened a mailing list thread about it : http://lists.infradead.org/pipermail/linux-riscv/2019-June/005129.html | 18:17 |
| tpb | Title: irq-sifive-plic + gpio-sifive break IRQF_ONESHOT (at lists.infradead.org) | 18:17 |
| daveshah | Back on the old core I had a lot of trouble getting the Maxim SPI-USB thing working | 18:17 |
| daveshah | That used ONESHOT I think | 18:17 |
| Dolu | Let's see if i'm right, or if i missed somehting | 18:17 |
| Dolu | Then that's probably the issue | 18:17 |
| Dolu | ONESHOT active low interrupt ? | 18:18 |
| Dolu | (not falling/rising) | 18:18 |
| daveshah | Yep, I think that's what it was | 18:19 |
| daveshah | https://github.com/torvalds/linux/blob/master/drivers/usb/host/max3421-hcd.c#L1943 | 18:20 |
| tpb | Title: linux/max3421-hcd.c at master · torvalds/linux · GitHub (at github.com) | 18:20 |
| Dolu | Basicaly the normal flow is : IRQ(mask(...)) -> threaded handle(...) -> unmask | 18:20 |
| Dolu | But with that bug, the interrupt is non stop trigerring : IRQ(...) -> IRQ(...) -> IRQ(...) -> IRQ(...) -> and never getting to the threaded handle | 18:21 |
| Dolu | Ahh, hm, quite different than the W5500. so maybe that wasn't the issue for that case. | 18:21 |
| keesj_ | https://www.seeedstudio.com/Perf-V-Based-on-Xilinx-Artix-7-FPGA-RISC-V-opensource-p-4058.html?utm_source=mailchimp&utm_medium=edm&utm_campaign=bazaar_0620 | 18:48 |
| tpb | Title: Perf-V Based on Xilinx Artix-7 FPGA RISC-V opensource (at www.seeedstudio.com) | 18:48 |
| keesj_ | I hope it is open hardware .. I would really fancy that right now. | 18:56 |
| futarisIRCcloud | keesj_: Yeah, I saw it yesterday. The high speed breakout seems useful. | 19:24 |
| keesj_ | but then .. ecp5 also exists... I wonder how the serdeses compare (for ddr3 type applications)... I think I need to see daveshah's code | 19:44 |
| keesj_ | futarisIRCcloud: it does not look very intimidating (like .. perhaps I can DIY a board like that) | 19:45 |
| keesj_ | http://shop.lambdaconcept.com/home/35-usb2-sniffer.html | 19:46 |
| tpb | Title: USB2 Sniffer (at shop.lambdaconcept.com) | 19:46 |
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