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| Dolu | futarisIRCcloud : https://www.mouser.ch/ProductDetail/Microchip-Technology-Atmel/ATWILC1000-MR110PB?qs=sGAEpiMZZMvNM%2Fd3q5fCVwZXj9etamV0iIjiArIcS%2FA= https://www.mouser.ch/ProductDetail/WIZnet/WIZ550io?qs=%2Fha2pyFadugKvUYGUvyio4zRdrfIj6Czg52guwTUL2E%3D https://www.mouser.ch/ProductDetail/Olimex-Ltd/ENC28J60-H?qs=sGAEpiMZZMuHH5xdpIBT%252BZAthlBATCnMXU1cVSxuqBY%3D https://www.mouser.ch/ProductDetail/Gravitech/USBHOST-4NANO?qs=%2Fha2pyFadujS5gErdC%252B2hKDL2XF | 09:03 |
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| Dolu | iZPjvzrEiH0lXWEc%3D | 09:03 |
| Dolu | Last link cuted : https://www.mouser.ch/ProductDetail/Gravitech/USBHOST-4NANO?qs=%2Fha2pyFadujS5gErdC%252B2hKDL2XFiZPjvzrEiH0lXWEc%3D | 09:03 |
| Dolu | It is very likely possible to get equivalent modules for much cheaper somewhere else | 09:04 |
| futarisIRCcloud | Ahhh. MAX3421E. I think I've seen similar modules on eBay for a little less. | 09:20 |
| Dolu | right, mouser isn't probably the best place to get breakout / modules | 10:56 |
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| RedMercury | How are extra connectors supposed to work? I see _connectors being passed through to the Platform object and into the constraint_manager->connector_manager, but I don't see any examples of actually using the pins defined in a connector | 16:13 |
| RedMercury | I've got a 1bitsquared hdmi board I want to try out with litevideo attached to my arty | 16:13 |
| keesj | RedMercury: what I have seen used is this construct https://github.com/enjoy-digital/litesdcard/blob/master/examples/arty.py#L32 | 16:34 |
| tpb | Title: litesdcard/arty.py at master · enjoy-digital/litesdcard · GitHub (at github.com) | 16:34 |
| keesj | e.g. define some pins and call https://github.com/enjoy-digital/litesdcard/blob/master/examples/arty.py#L87 | 16:34 |
| tpb | Title: litesdcard/arty.py at master · enjoy-digital/litesdcard · GitHub (at github.com) | 16:34 |
| felix_ | _florent__: is there a reason why the instructions how to build the lm32 cross compiler got removed from the litex readme? had to dig that out from the git history to set that up on my current machine | 16:51 |
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| ambro718 | _florent__: Hey, did you get a chance to look at my DMA code? | 17:08 |
| ambro718 | You said something about preparing a test bench :) | 17:09 |
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| _florent__ | felix_: i wanted to simplify things, vexriscv is now the default cpu and the toolchain can be downloaded easily | 17:56 |
| _florent__ | ambro718: yes sorry, you can look at the tests in https://github.com/enjoy-digital/litex/tree/master/test to see how to simulate a module | 18:02 |
| tpb | Title: litex/test at master · enjoy-digital/litex · GitHub (at github.com) | 18:02 |
| _florent__ | ambro718: there are also liteeth tests in https://github.com/enjoy-digital/liteeth/tree/master/test | 18:03 |
| tpb | Title: liteeth/test at master · enjoy-digital/liteeth · GitHub (at github.com) | 18:03 |
| ambro718 | ok thanks | 18:04 |
| _florent__ | ambro718: for your case, the idea would be to have two test benches, one for TX, one for RX | 18:04 |
| ambro718 | _florent__: just the DMA components, without covering the integration with the MAC? | 18:04 |
| _florent__ | for RX, you will generate a stream with a generator, like this for example: https://github.com/enjoy-digital/litex/blob/master/test/test_gearbox.py#L9 | 18:05 |
| tpb | Title: litex/test_gearbox.py at master · enjoy-digital/litex · GitHub (at github.com) | 18:05 |
| _florent__ | and you will have a checker that will verify the wishbone accesses | 18:05 |
| ambro718 | What would simulate the CPU which sets up the buffer descriptors in memory and does other interesting things with the DMA? | 18:06 |
| ambro718 | (reads and writes CSRs) | 18:06 |
| _florent__ | you can also have a generator in the testbench for that | 18:07 |
| _florent__ | for example: https://github.com/enjoy-digital/liteeth/blob/master/test/test_mac_wishbone.py#L14 | 18:08 |
| tpb | Title: liteeth/test_mac_wishbone.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 18:08 |
| _florent__ | https://github.com/enjoy-digital/liteeth/blob/master/test/test_mac_wishbone.py#L97 | 18:08 |
| tpb | Title: liteeth/test_mac_wishbone.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 18:08 |
| _florent__ | https://github.com/enjoy-digital/liteeth/blob/master/test/test_mac_wishbone.py#L116 | 18:08 |
| tpb | Title: liteeth/test_mac_wishbone.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 18:08 |
| ambro718 | How about read/write CSRs? | 18:09 |
| _florent__ | https://github.com/enjoy-digital/litex/blob/master/test/test_csr.py | 18:11 |
| tpb | Title: litex/test_csr.py at master · enjoy-digital/litex · GitHub (at github.com) | 18:11 |
| ambro718 | Thanks, I'll go making something. | 18:11 |
| felix_ | _florent__: ok. would still be useful to have that somewhere, but yeah it doesn't have to be in the main readme, since it's no longer the default being used | 18:19 |
| RedMercury | thanks tpb! | 18:20 |
| RedMercury | err, keesj | 18:20 |
| _florent__ | felix_: yes i agree, i'll make sure it's explained in a doc or wiki | 18:54 |
| felix_ | thx! | 19:01 |
| xobs | _florent__: could you please merge #2 in litex-boards? I think it's still unmerged | 21:24 |
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