*** tpb has joined #litex | 00:00 | |
*** futarisIRCcloud has joined #litex | 08:00 | |
*** futarisIRCcloud has quit IRC | 10:10 | |
*** futarisIRCcloud has joined #litex | 11:06 | |
*** futarisIRCcloud has quit IRC | 14:06 | |
*** ambro718 has joined #litex | 17:00 | |
ambro718 | I have two questions about the RX stream for LiteEthMACCore. | 18:59 |
---|---|---|
ambro718 | 1) Is last=1 guaranteed to be seen after first=1 or is it possible to see another first=1 without last=1 just before it? | 18:59 |
ambro718 | 2) What exactly does error mean? | 19:00 |
_florent__ | hi ambro718 | 19:35 |
ambro718 | Hi! | 19:36 |
ambro718 | I think I'm making good progress with the Ethernet DMA :) | 19:36 |
_florent__ | for 1), first is not use in LiteEth, only last | 19:36 |
_florent__ | great | 19:36 |
ambro718 | For error in RX stream I think I am responsible to detect any error and mark the packet as bad so it won't be given to the network stack in the OS. | 19:37 |
_florent__ | for 2) error is set to 1 if an error is detected in RX, IIRC it's mainly used for the CRC error | 19:37 |
_florent__ | yes, that's the idea | 19:38 |
ambro718 | Does liteeth check the length of received packets? | 19:38 |
ambro718 | Could it give huge packets in RX stream? | 19:38 |
_florent__ | yes we check the length: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/mac/sram.py#L85 | 19:40 |
tpb | Title: liteeth/sram.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 19:40 |
ambro718 | Great, than I won't worry about that. | 19:41 |
ambro718 | Also about error, I see its width is dw/8, is it correct to check just if it's not zero? | 19:42 |
_florent__ | but if you are replacing sram.py with a DMA, you'll have to handle it :) | 19:42 |
ambro718 | Ah yes I see now you pointed to the SRAM code. | 19:42 |
_florent__ | yes there is an error if != 0 | 19:44 |
ambro718 | _florent__: If you want you can check out the current code. Common and TX code is mostly written, but I never tried to compile it. https://github.com/ambrop72/liteeth/blob/dma/liteeth/core/mac/wishbone_dma.py | 19:49 |
tpb | Title: liteeth/wishbone_dma.py at dma · ambrop72/liteeth · GitHub (at github.com) | 19:50 |
ambro718 | I'd appreciate any hints or criticism :) | 19:50 |
ambro718 | Will this work: a.eq(b[0:14]) ? | 20:19 |
_florent__ | ambro718: thanks, i'll look a that tomorrow | 21:04 |
ambro718 | Great, if you can! | 21:04 |
ambro718 | I think I'll need to add the FIFOs manually though, they don't seem to be part of LiteEthMACCore, and sram.py seems to add them manually | 21:08 |
Dolu | futarisIRCcloud sirq is as far i know, Software IRQ | 21:38 |
*** ambro718 has quit IRC | 23:14 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!