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| xobs | mithro: I really really want to integrate wavedrom into litex. | 00:44 |
|---|---|---|
| mithro | xobs: Yes | 01:03 |
| mithro | xobs: There is already https://pypi.org/project/sphinxcontrib-wavedrom/ ... | 01:04 |
| tpb | Title: sphinxcontrib-wavedrom · PyPI (at pypi.org) | 01:04 |
| mithro | https://github.com/bavovanachte/sphinx-wavedrom/blob/master/sphinxcontrib/wavedrom.py | 01:05 |
| tpb | Title: sphinx-wavedrom/wavedrom.py at master · bavovanachte/sphinx-wavedrom · GitHub (at github.com) | 01:05 |
| xobs | I'm thinking we can add parameters to the csr functions that describe various bits and their meanings. | 01:05 |
| mithro | xobs: https://github.com/BreizhGeek/wavedrompy | 01:05 |
| tpb | Title: GitHub - BreizhGeek/wavedrompy: WaveDrom compatible python command line (at github.com) | 01:05 |
| mithro | WaveDrom compatible python module and command line. - This tool is intended for people who don't want to install the Node.js environment just to use WaveDrom as simple command line. | 01:06 |
| xobs | Oh perfect. | 01:06 |
| mithro | https://github.com/chiggs/mdx_wavedrom | 01:07 |
| tpb | Title: GitHub - chiggs/mdx_wavedrom: Python Markdown extension for inserting wavedrom waveform diagrams into markdown output (at github.com) | 01:07 |
| mithro | xobs: Have you seen https://kevinpt.github.io/symbolator/ and http://kevinpt.github.io/ripyl/ ? | 01:15 |
| tpb | Title: Symbolator Symbolator 1.0.2 documentation (at kevinpt.github.io) | 01:15 |
| xobs | mithro: I haven't, but I'm mostly excited about the register documentation ability of wavedrom, less excited about the waveform stuff. | 01:16 |
| mithro | xobs: Also looks like there is https://github.com/LudwigCRON/pywave -- This version is not a mere copy of the original one. | 01:17 |
| tpb | Title: GitHub - LudwigCRON/pywave (at github.com) | 01:17 |
| mithro | xobs: If your interested in Latex --> https://github.com/wifasoi/WaveDromTikZ :-P | 01:19 |
| tpb | Title: GitHub - wifasoi/WaveDromTikZ: An implementation of WaveDrom which outputs TikZ for use in LaTeX documents. (at github.com) | 01:19 |
| futarisIRCcloud | https://youtu.be/8iaNzCgKyJQ | 02:46 |
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| daveshah | _florent__: https://github.com/enjoy-digital/linux-on-litex-vexriscv/pull/1 | 09:31 |
| tpb | Title: Add support for ECP5 Versa-5G with Yosys/nextpnr/Trellis by daveshah1 · Pull Request #1 · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 09:31 |
| daveshah | One strange issue I've noticed is that when the system is cold (metaphorically if not thermally), occasionally the TFTP boot fetches an incorrect (too small) number of bytes - this seems to happen with both Diamond and Trellis | 09:32 |
| daveshah | doesn't ever happen once it's been run once or twice | 09:32 |
| daveshah | not sure if you've ever seen anything like this before? | 09:32 |
| daveshah | I also notice it prints a main RAM size of 262144KB which is double what it should be (but memtest passes, and the DTS only specifies 128MB, so it has no bearing on functionality) | 09:33 |
| keesj | what is the 25Mhz initial clock ? | 09:35 |
| daveshah | This controls the startup FSM that ensures the DDR clocks are properly synchronised | 09:36 |
| daveshah | It's a bit of an ECP5-specific idiom | 09:36 |
| Dolu1990 | daveshah: Nice :D | 09:46 |
| Dolu1990 | Maybe it is because the the IO range specification of the load/store ? | 09:47 |
| Dolu1990 | https://github.com/enjoy-digital/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenCoreDefault.scala#L134 | 09:47 |
| tpb | Title: VexRiscv-verilog/GenCoreDefault.scala at master · enjoy-digital/VexRiscv-verilog · GitHub (at github.com) | 09:47 |
| Dolu1990 | Ahh no, 0xB map the ethernet | 09:48 |
| Dolu1990 | I mean, the bootloader use 0xB0000000 or 0x30000000 to access the ethernet ? | 09:49 |
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| futarisIRCcloud | https://twitter.com/fpga_dave/status/1124974146625187840 does look good daveshah ... | 11:56 |
| futarisIRCcloud | I wrote something for the ecp5, using diamond yesterday, but couldn't get it to run (because of the license I was using) | 11:56 |
| futarisIRCcloud | It should be trivial to add ulx3s support, since that's already in litex. | 11:57 |
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| _florent__ | daveshah: i already had the netboot issue on the arty, so that's probably not specific to ecp5, i'll have a look | 19:24 |
| daveshah | Ah, interesting | 19:25 |
| daveshah | Even with the Versa board powered off for a long time, it didn't seem to come back (but my computer was on the whole time). It almost seems related to the TFTP server being "cold" | 19:26 |
| mithro | xobs: https://github.com/asyncvlsi/AMC | 20:54 |
| tpb | Title: GitHub - asyncvlsi/AMC (at github.com) | 20:54 |
| xobs | mithro: looks brand new! Similar to openram in that it's a tiler? | 20:56 |
| mithro | xobs: No idea, only found it 5 minutes ago :-P | 20:56 |
| xobs | Ooh, it does have one ruleset | 20:56 |
| mithro | http://avlsi.csl.yale.edu/research.php | 20:57 |
| tpb | Title: Yale Asynchronous VLSI (at avlsi.csl.yale.edu) | 20:57 |
| mithro | AMC is an open-source asynchronous pipelined memory compiler. AMC generates SRAM modules with a bundled-data datapath and quasi-delay-insensitive control. AMC is a Python-base, flexible, user-modifiable and technology-independent memory compiler that generates fabricable SRAM blocks in a broad range of sizes, configurations and process nodes. AMC generates GDSII layout data, standard SPICE netlists, Verilog models, DRC/LVS | 20:58 |
| mithro | verification reports, timing and power liberty models (.lib), and abstract placement and routing models (.lef). | 20:58 |
| xobs | Right now it looks like they target https://www.mosis.com/pages/Technical/Layermaps/lm-scmos_scn3me | 20:59 |
| tpb | Title: MOSIS Layer Map for SCN3ME and SCN3ME_SUBM (at www.mosis.com) | 20:59 |
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