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| keesj | somlo: when I was learning vhdl I had a great time doing test based development but in the last couple of month switching to verilog and migen I have a hard time determining how to start | 06:22 |
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| keesj | and .. I don't know how to test something like a serdes. | 06:28 |
| keesj | somlo: what is your background/experience in FPGA development? | 07:31 |
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| _florent_ | keesj: to simulate a serdes, you can use xsim | 10:04 |
| _florent_ | keesj: you generate a the top level with migen, and then stimulate if the way you would do with a traditional verilog approach | 10:04 |
| _florent_ | keesj: here is a testbench that could be useful for you: https://github.com/enjoy-digital/liteiclink/blob/master/sim/serwb.py | 10:05 |
| tpb | Title: liteiclink/serwb.py at master · enjoy-digital/liteiclink · GitHub (at github.com) | 10:05 |
| keesj | very cool | 10:39 |
| somlo | keesj: my background is mostly in software, networking, and sysadmin. I re-took a digital design /comp. arch ECE course sequence at the uni where I work (they use Verilog). | 13:32 |
| somlo | I'm a relative n00b when it comes to migen (and Chisel, for that matter) | 13:33 |
| keesj | I am kinda somewhere in between everything. | 16:32 |
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