| *** tpb has joined #litex | 00:00 | |
| keesj | my up5k based board is finally blinking | 10:37 |
|---|---|---|
| keesj | Now I will need to implement the usb stack thingy | 10:37 |
| keesj | steal from fomu / litex | 10:38 |
| somlo | Trying to debug a new cputype using "litex_sim.py", and Verilator crashes with "%Error: Verilog called $test$plusargs or $value$plusargs without testbench C first calling Verilated::commandArgs(argc,argv)". | 14:02 |
| somlo | I have some (not a lot) of experience with Verilator, but the testbench c++ files I used to write had a "main()" function whose "argc" and "argv" I could use to call into "Verilated::commandArgs()". | 14:02 |
| somlo | The litex-generated gateware simulation directory has "dut_init.cpp", and there's also "litex/build/sim/core/veril.cpp", but neither have a "main()" function from where I could call "Verilated::commandArgs()" -- any ideas? | 14:02 |
| somlo | nvm, figured it out, preparing a PR :) | 14:38 |
| keesj | cool | 14:41 |
| somlo | https://github.com/enjoy-digital/litex/pull/163 | 14:54 |
| tpb | Title: build/sim/core: Initialize Verilator commandArgs by gsomlo · Pull Request #163 · enjoy-digital/litex · GitHub (at github.com) | 14:54 |
| _florent_ | somlo: thanks, it's merged | 17:26 |
| somlo | _florent_: thanks! Now on to making sense of what's REALLY wrong with what I'm trying to do :) | 18:05 |
| keesj | I see having no board is bringing good to the community | 18:07 |
| somlo | keesj: I'm assuming if I tried to program the board with what I have right now, it'd be a bitstream-based implementation of a brick | 18:09 |
| somlo | so one way or the other, simulation is a necessary step :) | 18:10 |
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