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| xobs | somlo: I actually just set stuff up for Foboot. | 05:25 |
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| xobs | Everything is self-contained in https://github.com/im-tomu/foboot/tree/master/sw -- you might be interested in third_party/libbase/crt0--vexriscv.S | 05:26 |
| tpb | Title: foboot/sw at master · im-tomu/foboot · GitHub (at github.com) | 05:26 |
| xobs | I'm not sure why they have all those nops. I'm going to try removing them. Maybe it's a caching thing? | 05:26 |
| xobs | trap_entry probably doesn't need to be marked .global, but it'll generate a symbol so the debugger can read it. | 05:27 |
| keesj | xobs: it looks like a jump table . e.g. when the CPU gets an exception (or starts) it normally jumpt to an address in memory (the first one is typically the start addres) . I did some searching around in the code but did not find what the other addresses are supposed to be | 06:20 |
| keesj | normally for debug the nops are replace by jump/branch to current address . the readme has some hint on the resetAdress (ans so does some asm samples) in the code | 06:22 |
| keesj | https://github.com/slavaim/riscv-notes/blob/master/bbl/boot.md also has some notes (this is probably simply part of the risc v specs) | 06:27 |
| tpb | Title: riscv-notes/boot.md at master · slavaim/riscv-notes · GitHub (at github.com) | 06:27 |
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| xobs | keesj: that's a good guess. | 08:06 |
| xobs | maybe it could also be from the lm32 crt0.S, which is also 8 instructions (with two nop at the end)? | 08:07 |
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| somlo | xobs: thanks, I'll have a look -- turns out there's a bunch more stuff like per-arch functions for flushing [i|d]caches, etc. scattered throughout the headers that I need to come up with | 12:04 |
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