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| keesj | Been reading the ddr3 code and learning a lot. it remains intimidating/feature full so far | 11:53 |
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| somlo | _florent_: if I try changing the litex mem_map to use "rom" at 0x1000_0000 and "sram" at 0x1000_8000, and the resulting SoC "doesn't work" (no visible uart activity using vexriscv on nexys4ddr or ecp5versa) | 14:42 |
| somlo | am I looking for the rom address being accidentally hardcoded somewhere else in the code base, or is there any other potential problem I should assume? | 14:42 |
| _florent_ | somlo: each mem_map region should have a size of 256MB (0x1000_0000), there is a limitation on that | 14:44 |
| somlo | so if I want to free up 0000_0000 to 1000_0000 (rocket really really wants that for its own purposes), I should do 1000_0000 and 2000_0000 instead of going for smaller regions... | 14:44 |
| somlo | thanks, let me try test that out real quick :) | 14:45 |
| somlo | yeah, looks like sticking to full 256MB regions works -- thanks again! | 14:53 |
| somlo | _florent_: is that enforced by how slave wishbone interface addresses are decoded here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L36 ? | 15:10 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 15:10 |
| _florent_ | somlo: yes that's the limitation | 15:33 |
| mithro | https://usercontent.irccloud-cdn.com/file/89XhqTcT/image.png | 22:06 |
| mithro | LiteX/VexRiscv running Buildroot with Python on Renode | 22:06 |
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