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| keesj | how can i learn about the symulator? | 06:59 |
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| keesj | simulator that is | 06:59 |
| _florent_ | keesj: if you want to use the python simulations, you want follow https://github.com/enjoy-digital/fpga_101/tree/master/lab002 | 07:07 |
| tpb | Title: fpga_101/lab002 at master · enjoy-digital/fpga_101 · GitHub (at github.com) | 07:07 |
| _florent_ | keesj: if you want to use the verilator simulator, you can look at https://github.com/enjoy-digital/litex/blob/master/litex/utils/litex_sim.py and execute it | 07:07 |
| tpb | Title: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com) | 07:07 |
| _florent_ | it will just build as a classic target and will print the bios in your terminal | 07:08 |
| keesj | I had time yesterday again to start looking into litedram and saw the ddr simulation files also hence wondering about that | 07:23 |
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| somlo | _florent_: if I generate a standalone litedram controller (e.g., setting "cpu" to "None" in examples/nexys4ddr_config.py), is the initialization FSM automatically done in the gateware? | 21:34 |
| somlo | I notice the normal "external" dram_* signals, but also a set of "init_done" and "init_error" wires, and none of the (presumably large-is) set of wires that would allow an external CPU to manipulate initialization via MMIO registers | 21:36 |
| somlo | * large_ish set of wires | 21:36 |
| somlo | hmmm, digging through the generated verilog, init_done is assigned from soc_init_done_storage, which in turn is initialized to 0 and never changed... | 21:38 |
| somlo | so, the question is, can I generate a standalone litedram controller which exposes the necessary MMIO registers that I could manipulate to initialize it from a CPU that's not generated as part of LiteX ? | 21:39 |
| _florent_ | somlo: you can but this is not handled by the example design now | 22:39 |
| _florent_ | to do that, you need to set CPU to None, create a wishbone bus, add it as master and expose it | 22:39 |
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