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| xobs | Are there any examples of how to simulate a litex design? I'm not convinced the migen simulator is accurate, in particular FSM calculation, so I'd like to try a verilog simulator. | 03:56 |
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| xobs | What I can't figure out how to do is twiddle the csr values. Should I just expose the whole csr bus at the top? Or is there a preferred way to expose csr actions such as reading and writing? | 03:57 |
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| _florent_ | xobs: I added a test_car in litex, does it temps? Othewise, litex_sim van ne interesting for (simulate with verilator) | 07:05 |
| xobs | _florent_: I saw test_csr.py, which uses the Migen simulator. I've got this USB block that is working in migen simulation but not in hardware. litex_sim can handle CSRs? I was going to use verilator, iverilog, or xsim. | 07:07 |
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