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| acathla | tcal, how did you build the vexrisc + single-cycle mult? Where did you get the source (which branch) ? | 15:14 |
|---|---|---|
| im-tomu_ | [tcal-x] I started with the Litex submodule with prebuilt versions: https://github.com/litex-hub/pythondata-cpu-vexriscv (default branch), then loaded the submodules (again default branch/commit). Then go to pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/. Edit the makefile, either altering the target for VexRiscv_Min.v in place, or make a new target like VexRiscv_MinMult.v. Either way there will be more hacking to | 15:21 |
| im-tomu_ | [tcal-x] The existing make recipe for "Min" is: | 15:21 |
| im-tomu_ | [tcal-x] VexRiscv_Min.v: $(SRC) | 15:21 |
| im-tomu_ | sbt compile "runMain vexriscv.GenCoreDefault --iCacheSize 0 --dCacheSize 0 --mulDiv true --singleCycleShift true --singleCycleMulDiv true --bypass false --prediction none --outputFile VexRiscv_Min" | 15:21 |
| im-tomu_ | [tcal-x] Ooops, that's AFTER modifying it to get the single-cycle mult. -- both --mulDiv and --singleCycleMulDiv changed to true. | 15:22 |
| im-tomu_ | [tcal-x] Assuming you re-use the Min variant, then later you you need to change the -march option that you compile with from rv32i to rv32im in order for the compiler to generate actual mul instructions. | 15:24 |
| im-tomu_ | [tcal-x] In my run, with the single cycle mult, I only hit 44MHz, but the tool is conservative; it worked fine on my Fomu. The design used 97% of the logic cells, so it's a pretty tight fit. | 15:25 |
| im-tomu_ | [tcal-x] Oh wait, the make recipe I have above ALSO enables single cycle shift. That won't fit unless you do even more hacking. So I suggest you change it to "--singleCycleShift false". | 15:26 |
| im-tomu_ | [tcal-x] I forgot to mention, then just type "make VexRiscv_Min.v" --- you might need to remove the file first to force a rebuild since I don't think the Makefile recognizes the dependence on itself. | 15:28 |
| im-tomu_ | [tcal-x] (or just run the command in the recipe directly....) | 15:28 |
| acathla | tcal, so, how do you know it's using the hardware mult of the iCE40? | 15:32 |
| acathla | thank you for the explanations | 15:33 |
| im-tomu_ | [tcal-x] There is a resource usage chart that gets printed out from the tools. The mult uses 4 16x16 mults. Let me see if there's something to grep for in the Verilog. | 15:52 |
| im-tomu_ | [tcal-x] look for "MUL_HH".... | 15:53 |
| im-tomu_ | [tcal-x] (there are MUL_LL, MUL_HL, MUL_LH, and MUL_HH) | 15:54 |
| acathla | Info: ICESTORM_DSP: 0/ 8 0% I think that line tells us if hardware mult16 are used or not | 16:15 |
| im-tomu_ | [tcal-x] Yep | 16:19 |
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| tnt | acathla: make sure you have `-dsp` on the `synth_ice40` command of yosys | 17:57 |
| tnt | The Vex doesn't instanciate primitives, it relies on yosys to infer them from a `*` operator in verilog. | 17:58 |
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