Tuesday, 2021-01-26

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st-gourichon-fRegarding the issue I raised yesterday about https://github.com/im-tomu/foboot/blob/882ce04da8b97084ef95f5a967a0e2b7312b19c2/sw/src/dfu.c#L184 , is it useful that I submit a pull request?10:39
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acathlaanyone made the litex_bare_metal_demo work on a fomu?13:10
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tcalYes!17:14
tcalacathla: I did get the demo working.  At first, I thought it hung on the donut demo....but it was just that slow.  10 or 20s before the first donut is rendered.   So I rebuilt the VexRiscv with single-cycle mult, and got it close to 1 donut/second.   Then I rebuilt again with single-cycle shifter and got it to something like 1.4 donuts/second.17:16
tcalI loaded the code into the SRAM area, using LiteX serialboot instead of dfu-util.17:17
tcalI'm working on a blog post but having a hard time finding the time.   I can dump the details here if you're interested.  One issue I had to work around is that I had to revert to an older version of litex_term to get the serialboot to work: https://github.com/enjoy-digital/litex/issues/77317:20
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acathlawow wow wow tcal, how do you make a vexriscv do a single-cycle mult? And how can it fit in a fomu?21:29
acathlaAnd how do you send the demo via serialboot? At which address? It never worked for me.21:29
acathlaWe successfully built a demo that is working on fomu, by sending it in place of the bios and modifying the linker.ld too21:32
tcal:)  Single-cycle mult: the credit all goes to Charles Papon's VexRiscv.   All I had to do was turn on the option and rebuild it.   It already knew how to make a 32b multiplier out of 4 16x16 multipliers.    It didn't meet timing according to the P&R tools (44MHz vs 48MHz), but they're pretty conservative, and it worked on every actual Fomu that I tried it on.21:33
acathlasfl_payload = 64 is the key, cool :)21:33
tcalYeah, I was going to say, you can use the current litex_term.py if you hack a couple of the params :)21:34
acathlaMy problem is that I measure 156 cycles between two writes to a CSR (an UART), and there is nothing to multiply21:35
tcalThe Vexriscv minimal + single-cycle mult used 97% of the available logic cells, so it's pretty tight.21:35
acathlaAnd every operation seems to take way more than one cycle21:35
acathlatcal, with USB and debug?21:36
tcalAnd yes, to use serialboot I did need to alter the linker.ld in the demo.   In the #773 issue above, I describe a way that I added a new region.   But that isn't actually necessary; you can use the existing sram region, and just add an empty section at the beginning, say 0x3000, to avoid stomping on memory that the BIOS is using while doing the serialboot.21:37
tcalI don't think the vexriscv I used had the debug plugin enabled.21:40
tcalI'm not sure what you mean by USB.    The LiteX fomu.py has an ACM UART using ValentyUSB.21:41
acathlayes, that USB. it takes a lot of space21:41
acathlaAnd the debug is when you have a wishbone bridge21:42
acathlatcal, thank you, that issue discribes exactly all the problems I had.21:43
tcalYeah, I didn't try, but I don't think you can peek and poke using wishbone-tool with this build.   But not sure.21:43
acathlatcal, you can't with litex-board target, but you can with the one from the workshop. I added a few lines and it works fine. It should be optionnal in litex...21:44
tcalNote: to rebuild VexRiscv, you need sbt (the scala build tool), which is not small.   I barely understand it enough to do the rebuild; thank goodness Charles is very helpful.    But you don't need to rebuild if you're content with slow donuts :)21:45
acathlahttps://github.com/litex-hub/litex-boards/blob/929e55d7e62b7430b917d8a28604f315d4bb64b5/litex_boards/targets/fomu.py line 213 to 227 mostly21:47
acathlaslow donuts are OK, slow writes to CSR is not OK21:49
tcalAh, the old targets/fomu.py.   :)   The one still used in Fomu Workshop.21:50
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