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| mithro | xobs: https://wishbone-utils.rtfd.io | 00:48 |
|---|---|---|
| tpb | Title: Wishbone Utilities wishbone utils 0.5.0-9-g18511d7 documentation (at wishbone-utils.rtfd.io) | 00:48 |
| xobs | jnsquire: I find that there are several "bins" into which it'll fall. 99% actually converges sometimes. It's why I added the --seed option - sometimes changing the input verilog can affect the output timing. | 00:53 |
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| jnsquire | OK, it works! I was able to upload a foboot built with a DSP-using VexRiscv, and then upload and connect to a micropython image built with rv32im. Only thing I had to drop was the VexRiscv debug support. | 01:39 |
| jnsquire | ...and then I noticed the micropython binary didn't actually include any mul instructions, so I hacked in one, rebuilt and re-uploaded, and it works as expected. Huzzah! | 01:52 |
| xobs | Hooray! What does your config look like? | 01:53 |
| xobs | I added a crypto config to https://github.com/xobs/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenFomuCrypto.scala which ended up being 5050 LCs. I'd love to get that number down so I could fit in a fancier touchpad implementation. | 01:54 |
| tpb | Title: VexRiscv-verilog/GenFomuCrypto.scala at master · xobs/VexRiscv-verilog · GitHub (at github.com) | 01:54 |
| jnsquire | Vexriscv-verilog has: | 01:54 |
| jnsquire | VexRiscv_Fomu_Dsp.v: src/main/scala/vexriscv/GenFomuDsp.scala | 01:54 |
| jnsquire | So no hardware breakpoints or riscv debugging, unfortunately. Not sure if there's anything else that can be squeezed out to make more room. | 01:55 |
| jnsquire | === top === | 01:56 |
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| jnsquire | oops | 01:57 |
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| jnsquire | Would using the hard SPI blocks in place of the litex SPI help? | 02:04 |
| xobs | I was researching that. The hard spi blocks require you to program the registers first. | 02:07 |
| xobs | They're also single spi only, not quad spi. | 02:07 |
| mithro | jnsquire: I really want to move the spimem controller into it's own clock domain -- it should be possible to get the SPI controller to run at like >50MHz while the CPU core stays at 12MHz | 02:11 |
| jnsquire | CSR support seems to take up a fair bit of room. Maybe pack the functional bit in there together more tightly. | 02:11 |
| jnsquire | Is it possible to get 32-bit wide CSRs out of litex? | 02:13 |
| xobs | Yes, you can initialise BaseSoC | 02:14 |
| xobs | https://github.com/enjoy-digital/litex/blob/d92bd8ffaa9a9d1f3d51498c8e382f7041e69274/litex/soc/integration/soc_core.py#L94 | 02:14 |
| tpb | Title: litex/soc_core.py at d92bd8ffaa9a9d1f3d51498c8e382f7041e69274 · enjoy-digital/litex · GitHub (at github.com) | 02:14 |
| mithro | jnsquire: "Packing things together" might actually end up taking more resources depending on how things are encoded | 02:16 |
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| jnsquire | OK, looks like ditching the icache allows re-enabling the debug support, as well as allows for compressed instructions, and micropython build with rv32imc still seems happy enough. place and route completed pretty painlessly. | 04:21 |
| jnsquire | 5229 out 5280 LCs used | 04:21 |
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| mithro | xobs: Does the terminal do local echo? | 08:55 |
| xobs | mithro: no, it just displays what it receives from the other device. | 08:56 |
| mithro | xobs: `./target/debug/wishbone-tool --serial /dev/ttyUSB1 --server terminal --csr-csv ~/github/timvideos/litex-buildenv/build/ice40_hx8k_b_evn_base_vexriscv.minimal+debug/test/csr.csv` | 08:56 |
| mithro | xobs: If I hit characters, should I get anything? | 08:57 |
| mithro | xobs: As far as I can tell, it is doing local echo | 08:57 |
| xobs | I would imagine that you wouldn't get local echo, because of how the terminal is working. | 08:58 |
| xobs | What if you do "help"? | 08:58 |
| mithro | Well seeing as I get output when the device is not plugged in.... | 09:08 |
| mithro | Think it's a Linux verse windows difference? | 09:08 |
| xobs | Right, because I have it only take over the terminal once the bridge has been opened. | 09:08 |
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| xobs | mithro: I had someone test it on a debian-unstable system, and it behaved the same way as on windows. Maybe the csv parsing isn't working? Or maybe you were using the version of litex with a different register offset? | 12:27 |
| xobs | Also, as we were talking about this earlier today, here's the automatically-generated Rust documentation for Fomu: https://docs.rs/fomu-pac/0.0.3/fomu_pac/ | 12:40 |
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| tommythorn | Trying to update the boot loader on my PVT fomu fails on all platforms (Windows, macOS, multiple Linux). dfu-util fails in the middle with | 16:32 |
| tommythorn | state(10) = dfuERROR, status(8) = Cannot program memory due to received address that is out of range | 16:32 |
| tommythorn | This happens 40% in | 16:32 |
| tommythorn | Note, my last failure was on Windows 10 with the latest release of the fomu toolchain and the dfu from https://workshop.fomu.im/en/latest/bootloader.html#updating-the-fomu-bootloader | 16:35 |
| tommythorn | My other fomu didn | 16:39 |
| tommythorn | didn't have issues and show a very different LED pattern | 16:41 |
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