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| gurke_ | is there a way to generate a visualization of the fpga configuration (similar to the one in the nextpnr-gui) using the fomu-toolchain? or using some other cli utility? | 16:01 |
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| gurke_ | mithro: i have ported the two verilog examples from pr #124 to migen (to be used in the migen-section of the tutorial) | 19:06 |
| gurke_ | mithro: my first goal was, to have it completly without litex dependencies - thus i've copied parts of the board definition | 19:07 |
| gurke_ | mithro: https://github.com/mainini/fomu-workshop/tree/migen-example/migen | 19:07 |
| tpb | Title: fomu-workshop/migen at migen-example · mainini/fomu-workshop · GitHub (at github.com) | 19:07 |
| gurke_ | mithro: I don't think that's the most clever way - how would you integrate it to the workshop? | 19:08 |
| gurke_ | mithro: (and as a side question: i'm battling with the clock - I'm not able to request it from the platform and assign it to the SB_IOs... see commented out lines 69, 127 and 135) | 19:09 |
| jnsquire | In case anyone is interested, I've got VexRiscv generating verilog that uses the DSP to implement the multiplier (4/8 SB_MAC16 used). Required some fixes to the Mul16Plugin in VexRiscv. I'm still tinkering with the configuration to get a foboot build that passes the timing constraints. nextpnr is having a seriously hard time converging. | 19:13 |
| jnsquire | I've tried to enable the memory and writeback stages to see if that will help with the timing, but it ends up with 99% occupancy. Is it realistic to expect a successful built out of that? | 19:25 |
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| mithro | jnsquire: realistic? no -- might it still happen? maybe? :-P | 21:45 |
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| mithro | xobs: Look at the "continuous-documentation/read-the-docs" trigger on https://github.com/im-tomu/fomu-workshop/pull/124 ! | 21:59 |
| tpb | Title: Fix Verilog examples by mainini · Pull Request #124 · im-tomu/fomu-workshop · GitHub (at github.com) | 21:59 |
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