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| xobs | Hooray! Finally have an end-to-end demo of Foboot working! | 07:16 |
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| MadHacker | xobs: Yay! Good job. :) | 07:45 |
| xobs | MadHacker: thanks! | 08:00 |
| xobs | Finally figured out the SB_WARMBOOT construct. Turns out it's really five entries. | 08:01 |
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| MadHacker | Oh right? | 09:21 |
| MadHacker | Thought it was a four-image deal? | 09:21 |
| MadHacker | What's the fifth? | 09:21 |
| xobs | Yeah, the first entry is the "initial boot" entry, followed by four "reboot" entries. | 09:21 |
| MadHacker | Ahh. OK. | 09:21 |
| MadHacker | No way to loop back to the initial boot one? | 09:22 |
| xobs | If you set entry 0 and 1 to the same thing, that'll do it. | 09:22 |
| MadHacker | But that's just using two "slots" for the same image, no? | 09:22 |
| xobs | Correct | 09:23 |
| MadHacker | Ah, hold on, I see though - you can set the address for both to the same point in the flash, so you're not taking up more actual flash space. | 09:24 |
| MadHacker | So, no big deal. Fair enough. | 09:24 |
| MadHacker | The lattice tools actually generate a file with four images and a tiny bootloader that just samples two pins to pick which image to use and triggers the warmboot, now I look. | 09:27 |
| MadHacker | This option can be implemented by creating an applet from Deployment Tool as shown in Figure 12. | 09:27 |
| MadHacker | When this option is enabled in the applet, the iCE40 FPGA boots normally from power-on or a master reset | 09:27 |
| MadHacker | (CRESET_B = Low pulse), but monitors the value on two PIO pins that are borrowed during configuration, as | 09:27 |
| MadHacker | shown in Figure 11. These pins, labeled PIO2/CBSEL0 and PIO2/CBSEL1, tell the FPGA which of the four possible SPI configurations to load into the device. | 09:27 |
| xobs | I think that's what they mean when they refer to "coldboot", whereas "warmboot" means to start from the 0th image and prime the ability to reboot into image 1, 2, 3, or 4. | 09:30 |
| MadHacker | Aye, it's just that there's a standard 0th image in the lattice tools that makes it seem there are four images, not five. | 09:31 |
| MadHacker | I've never poked at this end of it, because my iCE40s have all been programmed in SPI slave mode. | 09:31 |
| MadHacker | (from Novena's own FPGA bit-banging) | 09:32 |
| tnt | AFAIR the up5k doesn't support the cbsel pins. | 09:32 |
| xobs | tnt: that's my understanding, too. | 09:33 |
| MadHacker | Nor does the HX from the above. It just supports a 0th image which reads them. | 09:38 |
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| tnt | the doc mentions cbsel for lp & hx. But excludes the up5k from that. | 09:40 |
| tnt | so if this is just a sw thing done by icecube, why is that ? | 09:40 |
| MadHacker | Perhaps a minimum image size thing in the ultraplus? | 09:40 |
| MadHacker | Or maybe they just literally never got around to building it. :) | 09:41 |
| MadHacker | Notice the wording above (C+P'd from the programming and configuration datasheet) - This option can be implemented by *creating* an applet from Deployment Tool as shown in Figure 12 | 09:42 |
| MadHacker | So I guess it builds it on the fly | 09:42 |
| xobs | Similarly, I saw a LEDD block (which they have a hard macro for in the Ultraplus) done in Verilog, presumably for older parts. | 09:43 |
| tnt | xobs: that's for the ultralite. | 09:44 |
| tnt | there is apparently a hardip ... but it's buggy so the tool replace it with a soft version using the 'hidden' logic in the smaller parts. | 09:44 |
| xobs | tnt: delightful | 09:44 |
| MadHacker | No harm in designing in some fault-tolerance like that. :) | 09:45 |
| MadHacker | CPU microcode patches are arguably similar. | 09:45 |
| tnt | if you look at the "iCE40 Ultra" line, the largest one is the only one that doesn't support the PWM ip. ... because all the LCs are "exposed" to the user, thereis nowhere to hide the soft ip. | 09:45 |
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| futarisIRCcloud | xobs: congrats on getting foboot working end to end. | 10:15 |
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| xobs | There, I added fancy LED effects. | 10:18 |
| tnt | hehe. | 10:20 |
| xobs | So in theory, Foboot (Rescue Mode) is Done. It can write a single image to offset 262144, and can reboot to that image. | 10:21 |
| xobs | You can use "dfu-util -e" to boot, or "dfu-util -D [image]" to write a new image. | 10:21 |
| xobs | It doesn't yet auto-boot. But baby steps. | 10:21 |
| futarisIRCcloud | xobs: Does it work fine on the hacker version? | 10:34 |
| xobs | futarisIRCcloud: I don't know! I should find someone with a development environment setup and ask. | 10:35 |
| xobs | rohitksingh_work: ping? | 10:35 |
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| rohitksingh_work | xobs: pong! | 10:43 |
| xobs | You've got a hacker setup, don't you? | 10:44 |
| rohitksingh_work | xobs: Yup, I've...last I had tried foboot, it wasn't enumerating correcrtly. Seems to have progressed quite a lot now. | 10:45 |
| rohitksingh_work | I'll try the latest design | 10:45 |
| tnt | arf, I wanted to give it a quick shot on the icebreaker but 48M vs 12M ... not so quick :p | 10:47 |
| xobs | tnt: Not super quick, but the default uses the PLL to generate 48M, so it's a simple change. | 10:48 |
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| tnt | yeah, trying to work that out now ... | 11:03 |
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| xobs | And I'm trying to work out how to re-integrate the BIOS code. | 11:07 |
| tnt | yeah when I build the bitstream with "./foboot-bitstream.py --rev icebreaker" ... I get build/gateware/top.bin but I guess I need to put some software somewhere for it to do anything ? | 11:15 |
| xobs | Sorry, I guess it's not quite there yet. I need to undo the random rom stuff that I've been developing with. | 11:18 |
| xobs | It's at the state right now where it's lots of little files. | 11:18 |
| xobs | https://gist.github.com/xobs/410328e964f78d37979e8f483e8310e1 | 11:18 |
| tpb | Title: Contents of matching rom ยท GitHub (at gist.github.com) | 11:18 |
| xobs | With "random.hex" being the output of "foboot-bitstream.py --export-random-rom-file random.hex" | 11:19 |
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| tnt | it's a shame this was never merged https://sourceware.org/bugzilla/show_bug.cgi?id=19921 | 11:34 |
| tpb | Title: 19921 enable specification of data width when writing verilog hex format (at sourceware.org) | 11:34 |
| xobs | I think my approach will be to modify the software Makefile a bit. | 11:34 |
| xobs | Yeah, shame. Though I'm rather proud of myself for writing that in Python and not C. | 11:36 |
| xobs | Anyway, I have a cellotape-and-string solution that I just need to build into the Python Makefile. | 11:37 |
| xobs | Once that's done, I'll switch gears and get to working on the case. | 11:37 |
| xobs | That hopefully will finally unblock everyone who has a Hacker version. | 11:38 |
| tnt | Oh, the led is breathing orange, that's a good sign. | 11:41 |
| xobs | ...i should add a csr to indicate the board revision. | 11:41 |
| tnt | mm, doesn't enumerate though so I guess I screwed something up somewhere. | 11:42 |
| xobs | Does it try, though? | 11:42 |
| xobs | The led is controlled by c code. | 11:42 |
| tnt | yes | 11:42 |
| tnt | [1601353.257338] usb 2-1: new full-speed USB device number 104 using xhci_hcd | 11:42 |
| tnt | [1601353.407326] usb 2-1: device descriptor read/64, error -71 | 11:42 |
| xobs | The d+/d- might be swapped. | 11:42 |
| tnt | is there any serial output ? | 11:44 |
| xobs | Hmm... Could also be a timing issue. I'm only trying it on a Raspberry Pi. | 11:44 |
| xobs | No serial output... I ran out of room. | 11:45 |
| tnt | mmm ... I just did a build --with-debug and, despite this one failing timing, it enumerates. | 11:45 |
| tnt | [1601577.651447] usb 2-1: Product: Fomu Bootloader (0) v0.1-40-gb40a9ba | 11:45 |
| xobs | Oh! Thats a good sign. | 11:46 |
| tnt | oh, wait nm ... it works without debug too. But I can't unplug/replug. It only enumerates if it's already plugged into USB when loading the bitstream. | 11:47 |
| tnt | and now it works all the time ... weird. | 11:51 |
| tnt | and dfu-util finds it :) | 11:51 |
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