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| Hammdist94 | after `abc -lut`, how can I get the lut depth of a design? | 08:06 |
|---|---|---|
| Hammdist94 | encountered bigger problem; `abc -lut 2` produces designs with lut3s | 09:13 |
| lofty[m] | I think the ABC output actually tells you the LUT depth of the design; I think it calls it `level` | 09:14 |
| lofty[m] | Can you pastebin your Yosys log? | 09:16 |
| lofty[m] | Hammdist94: ^ | 09:16 |
| Hammdist94 | ah yes, lev=6 in my case, when I switch to abc9 (abc regular does not show this). I wasn't using abc9 because it seemed to perform worse but now it seems abc is cheating by using larger luts than allowed so I will try to stick with abc9 for now | 09:20 |
| Hammdist94 | is there anywhere that I could find an example of a techmap file for luts? | 09:42 |
| Hammdist94 | I think I got it to make LUT2 by copying and editing a file from ice40 default techlibs | 09:58 |
| Hammdist94 | however it still doesn't show the LUT constants in the tabular output (nor blif) but only in verilog output | 09:58 |
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| lofty[m] | define "perform worse" | 12:51 |
| lofty[m] | Most likely ABC9 has actually found a lower-delay solution for your design, and this solution has less timing slack to recover area. | 12:52 |
| lofty[m] | (and a note on IRC etiquette: when replying to somebody make sure to mention their name, otherwise it takes three hours for them to respond) | 12:57 |
| Hammdist94 | that's certainly possible since plain abc does not show the lev value I cannot easily tell | 13:05 |
| lofty[m] | what's the output format you want to use? you keep talking about "tabular format"(?) | 13:12 |
| lofty[m] | (do you mean the output from stat?) | 13:12 |
| Hammdist94 | no, the output from yosys output_table command | 13:12 |
| Hammdist94 | it's easier to parse than verilog and doesn't contain aliased wire names but has no LUT constant information | 13:13 |
| Hammdist94 | oh, I found it can be added by editing the techmap definition of the lut: LUT2 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .C0(LUT[0]), .C1(LUT[1]), .C2(LUT[2]), .C3(LUT[3])); ... notice how the LUT table constants are fed as inputs which appear in output_table | 13:33 |
| lofty[m] | There...is no output_table command in yosys | 13:58 |
| lofty[m] | I guess you mean write_table? which is not really designed for that. | 14:00 |
| lofty[m] | If you want something parseable, why not use the JSON output? | 14:00 |
| Hammdist94 | ah yes sorry it's called `write_table` analogously to `write_verilog` | 14:01 |
| Hammdist94 | maybe I will try the JSON sometime | 14:02 |
| lofty[m] | That command has been basically untouched since 2017 | 14:03 |
| lofty[m] | it's true that parsing verilog is hard, which is why the JSON format is intended for "I want to process the output of Yosys" tasks. | 14:04 |
| lofty[m] | what's your synthesis target, by the way? LUT2 chips are not very common. | 14:04 |
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| Hammdist | lofty[m]: I was looking at dual LUT2 chips .. basically 74x153 .. until I realized the select lines are common to both of the "LUT2" in the package, making them not very useful for this purpose. now I'm thinking LUT3 with 74x151 | 17:17 |
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| lofty[m] | Hammdist: the thing is, using muxes as LUTs is kind of logic inefficient; you want to use them as muxes. | 19:53 |
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