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| Hammdist30 | I want to convert a verilog file into dffs and luts. this is almost what abc -lut does except the output from write_verilog is hard to parse and seems to contain optimizations whereby certain signal lines feed into clock enable and resets etc. these are shown as ifs in the output verilog. I would like it to map to plain FF with only clk, d, q. I | 17:30 |
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| Hammdist30 | also tried output_table but it doesn't contain the LUT constants (table). thanks for any advice | 17:30 |
| Hammdist30 | I made some progress on this; adding `dfflibmap -liberty cells.lib` where cells.lib contains a simplified DFF helps with one of the problems. still the verilog is not ideal to parse and the tabular output doesn't have the LUT constants | 17:39 |
| Hammdist30 | it seems it would be possible to parse out the constants IF I assume that the assign lut entries in the verilog file are in the same order as the luts in the table file | 17:46 |
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| lofty[m] | Hammdist: you are looking for the `dfflegalize` command | 19:22 |
| lofty[m] | and likely also a techmap file or two to convert the $lut and $DFF_P (or so) cells into your intended technology | 19:27 |
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