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| xiretza[cis] | <whitequark[cis]> "but check the specify block" <- the input to the last mux would correspond with the lowest delay in `specify`, right? I'm a little unsure because that's `I3`, while the simulation model controls the last mux with `I0` (not that I'm expecting this to necessarily be implemented the same as in hardware) | 09:56 |
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| lzrd | hello | 15:01 |
| lzrd | I have been playing with Yosys+nextpnr (using the oss-cad-suite) for a little rv32i project. I have a gowin FPGA so I am using project apicula. I observed that the fpga is running at 10 times lower frequency of 2.7 MHz. What could be going wrong here? Also sorry if wrong channel, please point me to the right one, newb here. | 15:04 |
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| bjorkintosh | lzrd: this is the right channel. just gotta lurk. | 15:21 |
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| whitequark[cis] | <lzrd> "I have been playing with Yosys+..." <- i would read the timing report, which contains the critical path | 17:41 |
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