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| famubu[m] | Thanks. Using abc9 instead of abc changes the output quite a bit (or so I think). | 04:39 |
|---|---|---|
| famubu[m] | What's the difference between the two? They are both the same tool, right? I guess it's used in different modes as was mentioned earlier. | 04:40 |
| famubu[m] | And device utilisation report from nextpnr for an trivial example I tried shows LUT5,6,7,8. But my FPGA has only LUT4. Is that a problem? | 04:42 |
| famubu[m] | Sipeed tang nano 9K | 04:42 |
| famubu[m] | is the board I'm trying. | 04:42 |
| famubu[m] | ---... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/LJjYWMtOCgeLmDUePoUEPQih>) | 05:36 |
| famubu[m] | Is there any way by which I can get around this? | 05:36 |
| famubu[m] | These were the yosys commands that I was using: https://bpa.st/4HBQ | 05:37 |
| tpb | Title: View paste 4HBQ (at bpa.st) | 05:37 |
| famubu[m] | Got error at command 10 (abc9). | 05:37 |
| famubu[m] | It comes from here, I guess: https://github.com/YosysHQ/yosys/blob/main/passes/techmap/abc9_ops.cc | 05:39 |
| famubu[m] | Is it that my design is too big to fit in my FPGA? | 05:39 |
| famubu[m] | Without the abc9 command the error doesn't show up. | 05:54 |
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| lofty | famubu[m]: so, there seems to be a fairly big misunderstanding going on here | 15:18 |
| lofty | If you run "help synth_gowin" you can see all the commands that it runs | 15:19 |
| lofty | Which includes pretty much all of the commands you're trying to run before it | 15:19 |
| lofty | If you're doing this to learn how a Yosys synthesis pass works, I'm happy to break everything down for you | 15:20 |
| lofty | But if you're just trying to synthesise things for your Tang Nano 9K, you only need to run synth_gowin | 15:21 |
| lofty | With that out the way | 15:22 |
| lofty | abc vs abc9: see https://github.com/Ravenslofty/yosys-cookbook/blob/master/misc/abc9.md | 15:23 |
| lofty | LUT5/6/7/8: it's true that Gowin devices have LUT4s, but they have muxes which let you combine LUT4s into bigger LUTs. so, no problem there. | 15:25 |
| lofty | And the ABC9 error: see https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html | 15:27 |
| tpb | Title: Setting up a flow for ABC9 - YosysHQ Yosys 0.44-dev documentation (at yosyshq.readthedocs.io) | 15:27 |
| lofty | (which is all done as part of the Gowin simulation library, so you can just do `read_verilog -lib -specify +/gowin/cells_sim.v`) | 15:29 |
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| Adrien[m] | Hi, about abc9 I'd like to raise a questionWith an intern we've noticed that activating abc9 with `synth_xilinx` can produce a much larger design, by something like 2.5x when summing LUT counts in final resource usage report (will be able to confirm once holidays are over). | 16:39 |
| Adrien[m] | I know abc9 flow is marked experimental, but to that extent really ? | 16:39 |
| Adrien[m] | RAM usage and processing time are also much higher. | 16:39 |
| lofty | Adrien[m]: I think I might know why | 16:46 |
| lofty | more or less, delay and area are inversely correlated; a lower-delay solution consumes more area because there is less timing slack available | 16:47 |
| lofty | my suspicion is that ABC9 has found a *much* lower-delay solution than ABC, and as a result, area went up | 16:47 |
| lofty | if you add `scratchpad -set abc9.D N` (where N is a delay target in picoseconds; I would say roughly half your intended clock period), then you should be able to recover a lot of area | 16:49 |
| gatecat | this might also be a consequence of synth_xilinx not flattening the design | 18:23 |
| gatecat | this means you generally have more, smaller modules, so the critical path that ABC sees is shorter | 18:23 |
| gatecat | and therefore it's more aggressively optimising for delay than it needs to, particularly as it can't see the "real" critical path as all it sees are the individual submodules | 18:23 |
| gatecat | you could compare the two with -flatten as well and see if there's a difference - usually I'd expect a decent improvement with abc9 on xilinx, because it tends to be more sensible about using wide LUTs (MUXF7/8) | 18:24 |
| Adrien[m] | lofty gatecat Thank you for the insight. We will have a look. | 20:11 |
| lofty | Adrien[m]: who's "we" in this instance? | 20:11 |
| Adrien[m] | The intern and me. Probably mostly me given that the intern will have his next year to begin | 20:13 |
| Adrien[m] | In the end we decided to always keep the hierarchy in test designs, because designs were not worse, and RAM usage and synth time were much lower. This is critical when doing synthe | 20:14 |
| Adrien[m] | ... synthesis within embedded system and under 512 MB of RAM total | 20:15 |
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