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| famubu[m] | Oh.. | 16:05 |
|---|---|---|
| famubu[m] | Can static timing analysis be done without cell library? | 16:05 |
| famubu[m] | I was looking at OpenTimer. And it seems to require cell library? | 16:06 |
| famubu[m] | Timing analysis is relevant for FPGAs as well, right? | 16:06 |
| famubu[m] | Wait.. Does nextpnr do timing analysis as well? | 16:15 |
| famubu[m] | I guess this is something related: share/yosys/gowin/cells_map.v | 16:19 |
| whitequark[cis] | nextpnr does timing analysis, yes | 16:19 |
| whitequark[cis] | timing analysis for FPGAs is done in a completely separate way from ASICs | 16:20 |
| famubu[m] | I guess opentimer is for ASIC then.. | 16:20 |
| famubu[m] | Is there some place I can read a little about differences in doing timing analysis for ASIC vs that of FPGA? | 16:21 |
| bjorkintosh | opentimer. perhaps if one is created for FPGA it should be called instead of opentimer, openheimer! | 16:21 |
| bjorkintosh | sorry famubu[m]. I know next to nothing myself. | 16:22 |
| famubu[m] | 😅 | 16:36 |
| famubu[m] | I found that tool upon a random google search: https://github.com/OpenTimer/OpenTimer | 16:37 |
| famubu[m] | Is yosys abc command for logic optimization not applicable for FPGA designs? | 16:51 |
| bjorkintosh | it has to be. | 16:57 |
| whitequark[cis] | abc is used for FPGAs | 17:15 |
| whitequark[cis] | just in different mode | 17:15 |
| famubu[m] | Oh.. sorry, I had been thinking the -liberty argument was mandatory for abc command. It's not. | 17:25 |
| lofty | Ideally abc9 is used for FPGAs | 18:05 |
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