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| Myrl-saki | How fast are the interconnects in other architectures? Seems like my design is mostly limited by routing. | 02:12 |
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| killjoy | ^ says everyone doing FPGA development ever. | 03:18 |
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| Myrl-saki | Hi, can someone review this please? I also added a description for the rationale. https://github.com/YosysHQ/yosys/pull/4000 | 14:53 |
| Myrl-saki | I just realized that this is probably not a full fix, as `$add` and `$sub` won't be able to unify with `share -aggressive` maybe. | 14:54 |
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| Myrl-saki | But for now, I think solving the `$lt` family is good enough. | 14:55 |
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