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| ikskuh | and another rubber ducking is necessary | 15:16 |
|---|---|---|
| ikskuh | i have a memory "reg [7:0] framebuffer [15:0];" with 32k bytes size | 15:17 |
| ikskuh | and i have a wire accessing this based on the x address of the vga | 15:17 |
| ikskuh | wire [7:0] current_color_index = framebuffer[img_x[7:0]]; | 15:17 |
| ikskuh | and i output that index to rgb in the pixel process | 15:17 |
| ikskuh | but it seems like it's only respecting the last 8 bytes or so in the buffer | 15:18 |
| lambda | you're only ever accessing one of the first 256 elements, is that intentional? | 15:18 |
| ikskuh | right now: yes | 15:18 |
| ikskuh | i have a small part that can read/write framebuffer memory via serial port | 15:19 |
| ikskuh | hm | 15:19 |
| ikskuh | maybe the writing is broken :D | 15:19 |
| ikskuh | is the framebuffer definition correct? | 15:21 |
| ikskuh | 15 bits of addresses for 8 bit data? | 15:21 |
| lambda | your buffer is 64KiB, not 32, but that shouldn't make much of a difference | 15:21 |
| lambda | I think that's how you do arrays in verilog? I'm honestly not sure though | 15:21 |
| ikskuh | oh right | 15:23 |
| ikskuh | i think i have to run a memtest first :D | 15:23 |
| ikskuh | to see if that part is working as expected | 15:23 |
| lambda | make sure it doesn't end up being blind to the problem :p | 15:24 |
| ikskuh | wdym? | 15:25 |
| lambda | it's fairly easy to design a memtest that isn't actually very good at detecting systematic errors | 15:26 |
| ikskuh | ah, yeah | 15:27 |
| ikskuh | i mean, "write random data to memory, read back, check if it's still the same" should do the trick | 15:27 |
| lambda | oh, if you're doing it from the outside, sure - but doing that on device would require an PRNG | 15:28 |
| ikskuh | yeah | 15:29 |
| ikskuh | okay, so my memory access is borked | 15:34 |
| ikskuh | hm | 16:59 |
| ikskuh | i feel like that whole RAM thing doesn't work | 16:59 |
| gatecat | looking over the backlog, it's not `framebuffer [15:0]` you want but `framebuffer [2**16-1:0]` | 17:00 |
| gatecat | it's a set of dimensions; not an address bus width | 17:00 |
| ikskuh | gatecat: thanks, i'll try! | 17:01 |
| ikskuh | can you explain the difference? | 17:01 |
| ikskuh | so | 17:01 |
| ikskuh | reg [TOP:BOT] framebuffer [IND_UPPER : IND_LOWER] ? | 17:01 |
| lambda | I guess think of it as `reg [WORD_HIGH : WORD_LOW] framebuffer [ARRAY_HIGH : ARRAY_LOW]` | 17:02 |
| ikskuh | wow ^^ | 17:03 |
| ikskuh | consistency \o/ | 17:03 |
| ikskuh | let's see | 17:03 |
| ikskuh | Warning: Replacing memory \fake_ram with list of registers. See src/top.v:151 "oh no"? | 17:04 |
| lambda | that's gonna cost you with 64KiB :D | 17:04 |
| ikskuh | yep | 17:05 |
| ikskuh | "please wait, we're synthesizing your fpga away" | 17:05 |
| lambda | there should be some output from memory inference further up detailing why various block RAMs don't work | 17:06 |
| ikskuh | ah | 17:07 |
| ikskuh | i probably have to enable the verbose output :D | 17:07 |
| ikskuh | i only have warnings/errors active right now | 17:07 |
| lambda | yeah | 17:07 |
| ikskuh | hm | 17:09 |
| ikskuh | not much smarter now | 17:09 |
| ikskuh | reg [31:0] ram [0:MEM_WORDS-1]; | 17:15 |
| ikskuh | interesting | 17:15 |
| ikskuh | this is from prjtrellis repo | 17:15 |
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| ikskuh | huuh | 17:25 |
| ikskuh | it looks like the memory_bram pass is never made? | 17:25 |
| lambda | what's your script? | 17:28 |
| ikskuh | connect_rpc -exec python3 scripts/genpll.py | 17:32 |
| ikskuh | read -sv src/*.v; | 17:32 |
| ikskuh | synth_ecp5 -top top -json build/top.json | 17:32 |
| ikskuh | it looks like theres a wrong order and the brams aren't resolved | 17:32 |
| ikskuh | where can i find the synth_ecp5 function/script? | 17:33 |
| ikskuh | weird | 17:38 |
| ikskuh | i removed my second bram definition | 17:38 |
| ikskuh | fixed the first one | 17:38 |
| ikskuh | now it seems to not replace it anymroe | 17:38 |
| ikskuh | pnr is running now | 17:38 |
| ikskuh | https://bpa.st/PA4A | 17:39 |
| tpb | Title: View paste PA4A (at bpa.st) | 17:39 |
| ikskuh | seems to do the right thing now | 17:39 |
| lambda | fyi, the synth_ecp5 pass is defined here: https://github.com/YosysHQ/yosys/blob/e14302a3ea2781dca2dfa3933be18c8e26654dce/techlibs/ecp5/synth_ecp5.cc#L29 | 17:42 |
| ikskuh | thanks! | 17:43 |
| ikskuh | pnr is still running /o\ | 17:43 |
| ikskuh | if i build the tools, do i have to pass optimization modes myself or are the toolchains built optimized by default? *thinking* | 17:44 |
| lambda | that's alotta luts for a VGA driver | 17:44 |
| lambda | what do you mean by optimization modes? | 17:44 |
| ikskuh | "-O3" and -"farch=native" | 17:47 |
| ikskuh | lambda: that's 32k | 17:47 |
| lambda | yosys defaults to -Os | 17:47 |
| lambda | nextpnr defaults to -O3 | 17:51 |
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| ikskuh | hm | 18:25 |
| ikskuh | something is wrong | 18:26 |
| ikskuh | pnr still running /o\ | 18:26 |
| ikskuh | lambda: aren't the luts required for interconnect of the RAM? | 18:27 |
| lambda | definitely not more than a few of them | 18:27 |
| lambda | for read/write enable conversion and such | 18:28 |
| ikskuh | hm, weird | 18:28 |
| ikskuh | reducing ram size to 256 bytes | 18:28 |
| ikskuh | reduced cell count by "yes" :D | 18:28 |
| ikskuh | Number of cells: 1474 | 18:28 |
| ikskuh | synthesis for 256 memory cells works | 18:51 |
| ikskuh | i can write them | 18:51 |
| ikskuh | Properties: ports=3 bits=65536 rports=2 wports=1 dbits=8 abits=13 words=8192 | 19:13 |
| ikskuh | this seems to generate all these wires :( | 19:13 |
| ikskuh | it seems to generate 2048 rams | 19:14 |
| gatecat | it looks like it's mapping to LUTRAM rather than BRAM | 19:14 |
| gatecat | what does the code look like ? | 19:14 |
| ikskuh | chaotic? | 19:16 |
| ikskuh | https://bpa.st/ZQAQ#1L57 | 19:16 |
| tpb | Title: View paste ZQAQ (at bpa.st) | 19:16 |
| ikskuh | line 88 (transitive 148) is where i read | 19:17 |
| ikskuh | and in the process at line 57 | 19:17 |
| gatecat | so, to map to BRAM, reads must all be in a clocked process | 19:18 |
| ikskuh | they are, right? | 19:18 |
| ikskuh | or is the rst a problem? | 19:18 |
| gatecat | rst is a problem | 19:18 |
| ikskuh | ah! | 19:18 |
| ikskuh | so synchronous reset is key? | 19:18 |
| gatecat | so the current_color_index won't map to BRAM | 19:18 |
| gatecat | no reset at all | 19:19 |
| gatecat | on the BRAM read port register | 19:19 |
| ikskuh | oh | 19:20 |
| ikskuh | i can make the reading part into a resetless process, right? | 19:20 |
| gatecat | yeah | 19:20 |
| gatecat | I'm also not sure if nested 'if's are alright for BRAM reads | 19:20 |
| gatecat | they should be but there have been bugs in various tools in the past | 19:21 |
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| ikskuh | let's see | 19:22 |
| ikskuh | i'm still a learner | 19:22 |
| ikskuh | commit, change, let's rock! | 19:24 |
| ikskuh | Number of memories: 0 | 19:25 |
| ikskuh | hm | 19:25 |
| ikskuh | should go up, right? | 19:25 |
| gatecat | no, that's about unmapped memories | 19:26 |
| ikskuh | ah, okay :) | 19:26 |
| gatecat | it should never be anything other than 0 post-synthesis, whatever happens, that's memories in the early part Yosys' IL which doesn't include BRAM etc | 19:27 |
| gatecat | mapping to BRAM should show "DP16KD" or "PDPW16KD" in the results | 19:27 |
| ikskuh | Bram port B1.2 has no sync reset input. | 19:27 |
| ikskuh | huh | 19:28 |
| Sarayan | what's a reset supposed to do on a memory? | 19:32 |
| Sarayan | I know on cyclonev it clears the output latch and nothing else, in particular not the memory contents | 19:33 |
| ikskuh | hm, now it complains "Bram port B1.1 has no initial value support." | 19:33 |
| gatecat | Sarayan: yeah, if memories have resets they're invariably just for the read latch | 19:33 |
| gatecat | but Yosys can't map them yet | 19:34 |
| gatecat | ikskuh: remove the `= 5'h00;` in `reg [4:0] vga_b_buf= 5'h00;` | 19:34 |
| gatecat | BRAM read ports don't support initialisation in ECP5 | 19:34 |
| ikskuh | ah | 19:36 |
| ikskuh | synthesis is suddenly down to "immediate" | 19:36 |
| ikskuh | :D | 19:36 |
| ikskuh | DP16KD: 26 / 208 ( 12%) | 19:37 |
| ikskuh | this looks good | 19:37 |
| gatecat | looks good! | 19:37 |
| ikskuh | doesn't work :D | 19:38 |
| ikskuh | seems to be stuck on 0x3F | 19:40 |
| ikskuh | wait | 19:42 |
| ikskuh | okay, this was definitly me being stupid | 19:45 |
| ikskuh | memtest seems to run now | 19:45 |
| ikskuh | i could hug you right now, gatecat! | 19:45 |
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| ikskuh | gatecat, lambda: thanks for the help! you made this possible: https://twitter.com/ikskuh/status/1477756558813585414 | 22:06 |
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