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| piegames | How can I do "negative" cover statements? | 14:03 |
|---|---|---|
| piegames | Like "if A happens, B should never happen" | 14:03 |
| piegames | Or on a more broader level, "this operation never takes longer than four cycles" | 14:03 |
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| mwk | piegames: that sounds like a straightforward assertion, assert !(a_happened && b)? | 17:24 |
| tnt | Is there any way to compare two synthesis results from a "topology" PoV ? Like the names of signals/cells is not stable obviously but looking at LUT INIT values, and how they're connected to each other and to FF, it should be possible to find equivalent to match the two graphs and find the parts that are different. | 17:34 |
| killjoy | This sounds like LEC. | 17:35 |
| killjoy | I don't know about opensource tools to do that, but this is what Cadence's Conformal LEC does. (They probably renamed it, they went through a rebranding a few years ago.) | 17:36 |
| tnt | yeah. I mean I know they are _not_ equivalent, but trying to find the differences. | 17:37 |
| killjoy | Yeah, you could ask lec these questions and it would show you. | 17:37 |
| killjoy | Names didn't really matter, it basically did graph comparisons. | 17:37 |
| tnt | I know I used a LVS tool to do SKY130 stuff, comparing the post-synthesis netlist with the extracted netlist after pnr. | 17:38 |
| tnt | Maybe I could use that. | 17:38 |
| killjoy | It's usually used to verify that synthesis didn't do something weird, but at a high level it really just diffs two designs. | 17:38 |
| killjoy | LVS != LEC, not sure if you can do that really. | 17:39 |
| killjoy | :shrug: I dunno. | 17:39 |
| tnt | Yeah I know they're different, but here I expect the LUT / FF to exist "as-is" exactly the same. LEC would check if they do the same thing (no matter how they are arranged), LVS would check if they're wired the same way. | 17:40 |
| killjoy | A quick google shows nothing in this realm. | 17:40 |
| killjoy | According to https://openlane.readthedocs.io/en/develop/#openlane-architecture it looks like yosys can do LEC? | 17:48 |
| tpb | Title: OpenLANE — OpenLANE documentation (at openlane.readthedocs.io) | 17:48 |
| killjoy | Digging deeper I don't see anything. I'm curious if you get LVS to work for this. | 17:53 |
| piegames | mwk: I was thinking to deep in implications so it actually took me a while to figure that one out. But yes, that works | 17:59 |
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| tnt | mmm ... lvs wants structural verilog only, so can't have constants in there, they need to be replaced with GND / VCC cells ... not sure if yosys can do that. | 19:56 |
| gatecat | tnt: hilomap | 19:56 |
| tnt | gatecat: Ah nice ! I had a look at the command list and missed it. | 19:58 |
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| tnt | Next issue is that it doesn't seem to look at params so I'd need to turn ever parametrized instance into something with a unique name encoding the params in the name ... | 20:58 |
| tnt | (realistically I'd just need the INIT for the LUT4, the rest doesn't matter much) | 20:59 |
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| killjoy | The more you go through this, the more I think you really need LEC. | 23:36 |
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