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| tnt | Is there an attribute I can set on a signal to tell yosys to actually generate and _use_ that signal as-is in logic whenever I use it and not try to optimize by looking at where that signal come frome etc ... ? | 21:16 |
|---|---|---|
| tnt | Like I have wire x = ~y; and then I use `x` in some expressions later, and I want it to not try to fold the inverter in there. | 21:17 |
| tnt | I tried 'keep' but that's not enough apparently :/ | 21:18 |
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| corecode | tnt: what would be the use case for this? | 21:26 |
| tnt | Guide yosys into doing "the right thing". | 21:27 |
| tnt | I want to do this: val_cur <= do_load ? val_load : (val_cur - 1); | 21:27 |
| killjoy | Yeah I don't understand why you would want to do that in this case. The synthesizer could very well fold your inverter downstream, or upstream, and what do you care as long as it's equivalent? | 21:27 |
| tnt | But for it to pack correctly, I have to write: val_cur <= do_load ? val_load : (val_cur + {N{do_load}}); | 21:27 |
| tnt | Err, wait, when simplifying my example, I inverted thing. | 21:29 |
| tnt | val_cur <= do_dec ? (val_cur - 1) : val_load; | 21:29 |
| tnt | val_cur <= do_dec ? (val_cur + {N{do_dec}}) : val_load; | 21:29 |
| corecode | oh otherwise it packs less compactly? | 21:30 |
| tnt | That only packs properly (1 LUT per bit) if do_dec is `1` when doing the decrement and `0` when doing the load due to the hardcoded carry chain. | 21:30 |
| tnt | And so if instead of using `do_dec` _exactly_ as I wrote it as a logic expression, yosys tries to optimize or unfold an inverter or something ... packing is screwed up. | 21:32 |
| killjoy | How wide is val_cur? and do_load is your 1 bit wire, right? | 21:38 |
| tnt | do_load is 1 bit. val_cur is 16 bit. | 21:38 |
| tnt | But that submodule ends up instanciated 32 times in a UP5k ... so wasting like 10% of the whole FPGA if packing for this is not done as it should. | 21:39 |
| corecode | good that you found a workaround | 21:39 |
| tnt | I didn't ... | 21:41 |
| killjoy | So, are you making an assignment or comparison with "val_cur <= do_dec"? | 21:42 |
| tnt | huh ? No. | 21:42 |
| killjoy | Are you wanting "if val_cur is less than or equal to do_dec?" | 21:42 |
| tnt | no. | 21:42 |
| tnt | it either loads a value or decrement by 1. | 21:43 |
| killjoy | I would be a lot more explicit in my code than this. | 21:44 |
| killjoy | You don't get points for being terse. | 21:44 |
| killjoy | You're trying to say "if do_dec is 1 decrement val_cur and assign it back, else give it val_load?" | 21:44 |
| tnt | That's the only way to write it so it packs properly .... | 21:44 |
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| tnt | Feel free to try and find another way : https://pastebin.com/Rbedy7J7 | 21:49 |
| tpb | Title: // yosys -p 'synth_ice40' t.vmodule top( input wire [31:0] ld_value, - Pastebin.com (at pastebin.com) | 21:49 |
| corecode | so you did find a workaround? | 21:49 |
| tnt | No. | 21:49 |
| corecode | ok i'm confused :) you said it packs correctly if you do this | 21:49 |
| corecode | what about instantiating the LUT manually? | 21:50 |
| tnt | As a separate module it works, but when the 'do_dec' signal doesn't come from outside, but from some internal logic, yosys tries to optimize it and merge it with the adder and screws things up. | 21:50 |
| corecode | ah! | 21:50 |
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| corecode | is the LUT the issue or the carry chain? | 21:50 |
| tnt | Which is why I want a way to 'fence' it. Tell yosys : "Ok, use 'do_dec' as is, don't touch it" | 21:50 |
| corecode | i don't think i can help at all, but I can learn :) | 21:50 |
| killjoy | This doesn't make sense to me. | 21:50 |
| killjoy | It shouldn't need to pack anything, you're just decrementing a 32 bit integer. | 21:51 |
| killjoy | Based on some signal. | 21:51 |
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| killjoy | I thought maybe your use of the ternary operator was confusing the synthesizer. | 21:52 |
| killjoy | But you're saying the lower code doesn't work right? | 21:52 |
| corecode | i'm assuming it prepares the LSB in one LUT and then does the carry chain separately | 21:52 |
| killjoy | Oh wait. | 21:52 |
| tnt | It "works" as in the logic is "correct" but it uses twices as many LCs at the top one. | 21:52 |
| killjoy | *sigh* let me attempt to dig into brain cells from 10 years ago. | 21:52 |
| killjoy | I think it's because you're implying latches, but let me try to remember. | 21:53 |
| tnt | I can assure you it's not. | 21:53 |
| corecode | so what do the two LUTs do? | 21:54 |
| corecode | one for the mux, the other for ~do_dec being inverted again? | 21:54 |
| tnt | two LUTs ? | 21:54 |
| corecode | you said it allocates two LC | 21:54 |
| tnt | per bit. | 21:54 |
| corecode | is that LUT + carry element? | 21:54 |
| tnt | No, it will use 1 LC per bit to implement the decrement and then another LC to do the mux. | 21:55 |
| killjoy | Yeah ok it's not that. | 21:55 |
| corecode | huh ok | 21:55 |
| tnt | while in reality you can do both theses functions in the same LC. | 21:55 |
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| corecode | does it use the carry chain of the LC? | 21:55 |
| tnt | yes | 21:55 |
| corecode | or does it do a plain LUT ripple | 21:55 |
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| corecode | aha, so it fails to merge carry chain and mux LUT | 21:56 |
| corecode | surprising | 21:56 |
| tnt | well the ice40 has a very rigid carry structure. | 21:56 |
| tnt | and it's only mergeable when the 'control' signal has value '1' when doing the decrement and value '0' when doing the load. | 21:57 |
| tnt | (you'd have to go dig up the ice40 internal structure to understand why ... a bit late here for me to explain all the details ... ) | 21:58 |
| corecode | ok | 21:58 |
| corecode | i'll have a look out of curiosity | 21:58 |
| corecode | so even if you'd instantiate a SB_CARRY and a SB_LUT4, it might not get merged | 22:00 |
| corecode | i mean, co-located | 22:00 |
| tnt | well ... yeah, if I instanciate primitives manually I'm sure it'd work ... | 22:01 |
| tnt | but that's a major pain. | 22:01 |
| corecode | or not... | 22:01 |
| corecode | or does nextpnr do the co-locating? | 22:02 |
| corecode | the tech library docs are not very good in this regard | 22:02 |
| tnt | nextpnr does the colocating. | 22:03 |
| tnt | if the SB_CARRY in/out connect to the righ tports of the SB_LUT4 for it to go there. | 22:03 |
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| killjoy | Eh, it's been too long for me, and I never did an FPGA project, just ASICs. | 22:04 |
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