| *** tpb has joined #photonsdi | 00:00 | |
| Bertl_oO | but I would test it, because there is a chance that the bank doesn't really 'float' even with tristate | 00:00 |
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| Bertl_oO | should be rather trivial to test though | 00:00 |
| felix_ | can be tested on aux0/aux1/rxd/txd | 00:01 |
| felix_ | oh, wait, those are on the 3v3 rail | 00:18 |
| *** RexOrCine|away is now known as RexOrCine | 00:39 | |
| *** se6astian|away is now known as se6astian | 08:08 | |
| *** Bertl_oO is now known as Bertl_zZ | 11:10 | |
| *** RexOrCine is now known as RexOrCine|away | 15:11 | |
| *** se6astian is now known as se6astian|away | 16:17 | |
| *** se6astian|away is now known as se6astian | 17:35 | |
| felix_ | so i worked on most of the todos regarding the pcb | 17:38 |
| felix_ | some footprints might still need some fine-tuning | 17:38 |
| se6astian | grea | 17:47 |
| se6astian | t | 17:47 |
| se6astian | is a new pcb required for software dev or is that just for the future production model? | 17:47 |
| felix_ | only thing i didn't do was connecting the power good signals to the lower connector. would have enough pins for that and the routing congesting isn't too bad, but at least for the power good pin of the stepdown that feeds the ldos for the gtps the problem is that it has a pullup to the 1,35v rail and connecting th epullup to some other rail probably causes more problems than it solves things | 17:48 |
| felix_ | i'll do the initial photonsdi bringup on the board with the trenz module | 17:49 |
| felix_ | i'm not sure how much pain it'll be using the current module connected to the camera; there's the power sequencing problem | 17:50 |
| felix_ | so question is if it would be better to not solder the sdi chips on the current revision and do the next revision after the clock generator bringup was successful | 17:51 |
| felix_ | i put the ~init and the done signal of the fpga on the lower connector, so the camera can delay the start of configuration and see if the configuration was successful | 17:55 |
| felix_ | couldn't really get the ~program signal no the connector; already too much routing congestion and the ~init pin was more important to wire to the camera | 17:56 |
| Kjetil | What is the power seq. problem? | 17:59 |
| felix_ | problem with the first prototype of the axiom photonsdi hw was that the 5v rail is always powered (i though it wasn't) and the flash is on the 3.3v rail that can be switched off. so the fpga tries to talk to the flash while the flash isn't awake yet, so the configuration fails | 18:01 |
| felix_ | but with wiring the ~init signal and all enables of the stepdown converters, that problem should be gone | 18:02 |
| Kjetil | And it doesn't retry ? | 18:02 |
| felix_ | doesn't seem so | 18:03 |
| Kjetil | oh well. not the most serious problem | 18:03 |
| felix_ | yeah, it doesn't prevent the prototype from being used for tests, but for using it in the camera it'll be a bit of a pain | 18:04 |
| Kjetil | hm.. so the FPGA doesn't have internal POR monitoring? | 18:04 |
| felix_ | it does, but probably the flash takes longer than the fpga likes | 18:04 |
| Kjetil | What kind of package did you use on the flash? | 18:05 |
| felix_ | soic8w | 18:05 |
| Kjetil | so if you really want to you can lift a leg on the package and wire in a LDO from 5v | 18:06 |
| felix_ | yeah, that might be a workaround | 18:07 |
| felix_ | hm, should i add 2 or 3 resistors to some io bank that the fpga gateware can detect which revision it is or should we rely on the camera telling the fpga that/loading a bitstream that is specific for that version? | 18:19 |
| *** Bertl_zZ is now known as Bertl | 18:21 | |
| felix_ | morning Bertl! | 18:21 |
| Bertl | the board revision should be part of the eeprom already on the board, so I don't think it makes too much sense to encode it in the FPGA | 18:23 |
| Bertl | OTOH, you have plenty of unused pins you can connect to either GND or VCC, so if you like to make it identifyable, why not | 18:24 |
| Bertl | doesn't make much sense to use resistors though, you can easily probe for GND, floating or VCCIO connections | 18:25 |
| felix_ | i'd add pads for 100R resistors to ground | 18:25 |
| felix_ | the resistor is for the case when a pin gets accidentially configured as output and that differently populated boards cand be distinguished (so not only depending on the board revision) | 18:26 |
| *** se6astian is now known as se6astian|away | 22:13 | |
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