Sunday, 2018-07-15

*** tpb has joined #photonsdi00:00
*** Bertl_oO is now known as Bertl_zZ06:09
KjetilHow doe sthe cap. placement affect the panelizablity of the PCBs ?10:38
felix_well, if the ceramic capacitors are too cloese to a v-cut or mousebite and the boards get separated after being populated, the ceramic capacitors get quite a bit of mechanical stress which may cause failure and those ofter fail with a short11:10
felix_*often11:10
Kjetilyeah. But will typically have frame around the board for the pick and place to grab onto anyway even if it is single PCBs per panel11:11
felix_the axiom pcbs i saw at the office didn't have a frame around them and also weren't in a panel11:15
felix_i usually don't place anything too close to the board edge, but this board was rather space-constrained...11:18
*** Bertl_zZ is now known as Bertl13:24
Bertlit's not critical, even if we do mouse bites (for a panel) we do it in such way that it can be depanelized without much stress for the boards13:26
felix_ok13:28
felix_just wanted to make sure before the boards get manufactured13:28
felix_now the gtp power supplies are routed and the footprints of the linear regulator is fixed14:22
felix_the footprint of the switch mode regulator still needs some patching and then the 75 ohm parts need to be routed14:22
felix_now only the 75 ohm parts are still unrouted15:46
felix_https://i.imgur.com/Ufjuoeb.jpg15:47
Kjetilremember to void the ground plane underneath the 75ohm part16:47
felix_huh, no ground plane? i'm still undecided if i try to fit a coplanar waveguide configuration in there or just route the few millimeters as microstrip line. both heve a ground plane beneath17:09
KjetilThere should be a ground plane but probably not in the next layer17:10
felix_sure, add a cutout benaeth the capacitor and pin of the hdbnc connector, to avoid too big impedance mismatch17:10
Kjetilyep17:10
felix_i did the calculations for layer 2 as ground plane and got sane values for the geometry17:11
Kjetilsure you won't get too high capacitance?17:12
felix_i'm not very used to route non-differentail high speed traces though17:12
felix_hmm, good question17:12
felix_i put the values into the saturn pcb calculator and changed the geometry until i got about the impedance i wanted17:13
KjetilI guess the only way to find out is to route the board and measure it17:13
Kjetilbut antipads for the centerpin and capacitor I guess is a given anyway17:14
felix_yep17:14
KjetilAnd it's a minor modification to the board for the next batch anyways. As long as there are no traces in that area17:15
felix_there are no near traces on the top layer17:16
KjetilI was thinking in the layers underneath the HDBNC connectors17:16
felix_there are no components or traces17:17
*** se6astian|away is now known as se6astian17:43
felix_board is fully routed \o/18:10
felix_now some food ;)18:10
se6astianhurray!18:30
Kjetil\o/18:36
felix_is there some logo that i should add to the slkscreen?19:15
felix_*silkscreen19:15
felix_http://gerblook.org/pcb/s4L8MhjxyP6RkgcEZbgxGT19:35
tpbTitle: GerbLook (at gerblook.org)19:35
felix_Bertl: http://sigsegv.notmysegfault.de/intern/AXIOM-photonSDI-hw.zip the gerber export. i hope i checked the right boxes for the drill files19:38
felix_i did some slight changes on one of the power supply polygions after the gerber export, but just some minor details20:15
felix_uploaded a new version at the same url20:22
felix_Bertl: do you know if there's some recommended geometry for the antipads in the planes below the capacitor between the hdbnc connector and the sdi chip? didn't find anything really useful with a few minutes of research :/20:26
felix_enough for me for today; i'd say the board is already looking quite nice20:33
*** se6astian is now known as se6astian|away21:13

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