| *** tpb has joined #photonsdi | 00:00 | |
| *** Bertl_oO is now known as Bertl_zZ | 04:49 | |
| *** se6astian|away is now known as se6astian | 07:06 | |
| *** se6astian is now known as se6astian|away | 07:14 | |
| *** Bertl_zZ is now known as Bertl | 13:26 | |
| felix_ | routing the 3.3v to the parts except the fpga and the flash was surprisingly easy. now only the footprints of the voltage regulators need to be fixed and the 75 ohm sdi traces need to be routed | 13:52 |
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| Bertl | great! | 13:53 |
| felix_ | i thought that the 0.5mm wide trace wouldn't fit on the bottom layer beneath the fpga, but i still tried and it looked much better than i expected | 13:54 |
| felix_ | the pcbs will be assembled pcb by pcb and not multiple pcbs in a panel and then snapped into the single pcbs, right? | 13:55 |
| felix_ | at least that was my assumption when placing some of the ceramic capacitors... | 13:55 |
| felix_ | gotta go now, bbl | 13:56 |
| felix_ | hmm, i'm not entirely sure if this is good or not so good, but i think it improves things a bit https://github.com/felixheld/AXIOM-photonSDI-hw/commit/5fd8571b89b1424ad28caad16a045ae958e87a9b now the 3.3v is basically a ring on the bottom layer | 14:24 |
| tpb | Title: route the 3.3V additionally via another path to lower impedance · felixheld/AXIOM-photonSDI-hw@5fd8571 · GitHub (at github.com) | 14:24 |
| felix_ | and i'm afk again; this time probably for a few hours | 14:24 |
| felix_ | but yeah, this design was surprisingly routeable on only 4 layers without having to cut too many corners | 14:26 |
| felix_ | only thing i couldn't do was routing the recovered clock output from the sdi equalizer to the clocking chip, but i don't think that that connection was essential | 14:27 |
| felix_ | the rest only needed some careful planning and completely reworking the bank and io pin mapping on the fpga to get better routability... | 14:29 |
| *** Bertl is now known as Bertl_oO | 14:58 | |
| *** RexOrCine is now known as RexOrCine|away | 21:25 | |
| felix_ | i left the (tented) vias to the second gtp clock input, so in the worst case a crystal oscillator could be bodged into the design, after removing the solder mask on those two vias | 21:52 |
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