| *** tpb has joined #photonsdi | 00:00 | |
| Bertl_oO | felix_: at least for the other modules with FPGA we decided to simply put the jtag on the 'medium speed' GPIO pins from the MachXO2 interface | 00:26 |
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| Bertl_oO | now whether you want to go for a flash and either program that via the jtag too (indirect programming should work) or also expose the flash via SPI (in addition to jtag) is kind of up to you | 00:27 |
| Bertl_oO | personally I'd suggest to avoid the jtag connector on the AXIOM Plugin (uses up a lot of space) and instead use the MachXO2 connection for this | 00:28 |
| Bertl_oO | for testing and/or development you can still have your own PCIe to JTAG 'adapter' if you like, but that's just my two euro cents :) | 00:29 |
| felix_ | ok | 00:29 |
| felix_ | does the jtag functionality for the axiom already exist? | 00:30 |
| felix_ | i mean is it usable? | 00:30 |
| Bertl_oO | kind of, we did that (in a hackish way) for the USB3 plugin | 00:30 |
| felix_ | ok | 00:31 |
| Bertl_oO | and that already worked to get a test bitstream generator onto the MachXO2 on the USB3 plugin via the AXIOM Beta routing fabric (MachXO2 on main board) | 00:32 |
| felix_ | ok, then i'll probably add a flash to the board and route the jtag to the axiom connectors | 00:33 |
| felix_ | is there any pinout mapping for the jtag or doesn't it matter how it is routed | 00:34 |
| Bertl_oO | the hack is currently a direct pass through of signals, so it easy to adjust for almost any mapping | 00:35 |
| Bertl_oO | so just to clarify, the procedure for the USB 3.0 plugin is like this: | 00:38 |
| Bertl_oO | 1) the PIC for the RFW is programmed via ICSP | 00:39 |
| Bertl_oO | 2) the RFW (MachXO2) is programmed via JTAG (from the PIC) | 00:39 |
| Bertl_oO | 3) the passthrough connects some other pins from the PIC to allow JTAG on the USB3.0 module | 00:40 |
| Bertl_oO | 4) the same JTAG programming happens for the MachXO2 on the USB 3.0 module (via PIC) | 00:40 |
| Bertl_oO | (the PIC is accessed via I2C once it has been programmed) | 00:41 |
| *** Bertl_oO is now known as Bertl_zZ | 03:07 | |
| *** se6astian|away is now known as se6astian | 07:18 | |
| Kjetil | Passive serial programming is probably way easier | 08:57 |
| Kjetil | I guess you should consider the programming/boot time of each solution. And maybe add strapping options for other modes | 09:10 |
| Kjetil | I'm guessing that the Artix bitstream is quite a lot bigger then the MachXO2 stream | 09:13 |
| *** Bertl_zZ is now known as Bertl | 09:45 | |
| *** Bertl is now known as Bertl_oO | 10:36 | |
| felix_ | well the jtag version would have a flash and would only use the jtag to update (or unbrick) the module. loading the bitstream via bitbanged jtag every time the camera is switched on wouldn't be a good idea | 16:29 |
| Bertl_oO | can be done quite efficiently, also it could be uploaded via SPI | 16:32 |
| Bertl_oO | but of course, the flash is an option too | 16:33 |
| felix_ | i'd say either upload the bitstream every time the camera is switched on with this module installed and no flash or flash and jtag emulation for updating/unbricking | 16:34 |
| felix_ | ah, or did you mean with use the low speed pins on the axiom connector for jtag to put jtag there in addition to the slave serial configuration interface of the fpga? | 16:35 |
| Bertl_oO | the 'low speed' is more a 'medium speed' so you can get up to 500Mhz easily there :) | 16:36 |
| felix_ | ah, ok | 16:36 |
| Bertl_oO | jtag can run at 50MHz and the RFE can basically use each cycle if done properly | 16:36 |
| Bertl_oO | assuming the Artix 7A50T we have 17Megabit config data IIRC | 16:37 |
| Bertl_oO | so it would probably take less than half a second to configure it via JTAG | 16:38 |
| Bertl_oO | but SPI is even faster | 16:38 |
| Bertl_oO | note that there is no problem to have both, you probably have more than enough GPIO pins for the plugin (8 per slot without I2C) | 16:38 |
| felix_ | yep | 16:47 |
| felix_ | but if i'd put a flash on the board, i'd have to put a multiplexer on the board and some logic controlling that multiplexer and the configuration mode pins | 16:48 |
| Bertl_oO | if you decide you want an on-board flash, I'd suggest to stick with JTAG and reconfigure tha flash via that | 16:52 |
| felix_ | yep. still not sure though if i should put a flash on the board or net | 16:54 |
| felix_ | *not | 16:54 |
| se6astian | in terms of hardware assembly complexity I guess the flash chip is a rather dense bga, so I would rather avoid it | 17:11 |
| se6astian | the FPGA will already be a challenge to place | 17:11 |
| Bertl_oO | SPI flash is 8 pin, but it is usually larger | 17:14 |
| Bertl_oO | i.e. they are typically at least 6x6mm often more | 17:17 |
| se6astian | ok that doesnt sound too bad | 17:18 |
| *** se6astian is now known as se6astian|away | 21:48 | |
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