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| felix_ | i wonder how the bitstream for the axiom sdi board should be updated in the field. just configure the fpga on the module from the axiom and don't put a flash on the module? with this updating the bitstream would just be replacing a file on the camera and wouldn't involve any special jtag adapter | 21:37 |
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| Kjetil | Is there any suitable connections for loading the FPGA? | 21:45 |
| felix_ | there are some connections through the machxo2(?) chips on the camera | 21:46 |
| Kjetil | Are those connectable to the programming interface on the FPGA? | 21:47 |
| felix_ | i'll be designing the board, so yes | 21:48 |
| felix_ | there are 2x 8 connections available for slow-ish interfaces | 21:49 |
| felix_ | if we put a flash on the board, we'd have to speak jtag from the axiom to the sdi module to be able to unbrick it in case of a bad image in the flash | 21:51 |
| Kjetil | ah. you aren't using the plugon module in the final design | 22:08 |
| Kjetil | ? | 22:08 |
| felix_ | yep, the redesign will be without the fpga module, but with the fpga directly on the same board as the sdi chips | 22:18 |
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