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| LnnrtS32 | Hey, I have an orangecrab v0.2.1 (ECP5 and DDR3 RAM) running at 60MHz sysclock. When writing to SDRAM with a DMA I see that throughput maxes out at around 12.5MiB/s. (I already removed the l2 cache since that was reducing throughput quite a bit). Can someone explain me why it is that slow? The way I understand it is that the PHY is running at | 09:45 |
|---|---|---|
| LnnrtS32 | 2x60MHz DDR with 16 data width which would result in 480MB/s. Of course this is not achievable as an actual throughput but the gap seems quite large. Why is this? | 09:45 |
| LnnrtS32 | Related question: Why is cmd_delay defined like this? | 10:03 |
| LnnrtS32 | cmd_delay = 0 if sys_clk_freq > 64e6 else 100 | 10:03 |
| LnnrtS32 | Why is there a sharp edge? | 10:03 |
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