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| LnnrtS | Hello! Is anyone familiar with litesdcard and would answer some of my questions? | 11:23 |
|---|---|---|
| LnnrtS | Or is there another place that is more suitable to ask such questions? | 11:23 |
| Flea86 | LnnrtS: What was your question? | 11:28 |
| LnnrtS | I wonder if its feasible to run parts of litesdcard on a faster clock to improve performance for longer sequential accesses. My initial approach was to remap core and phy into the fast clock and cdc the streams but that then cdc for the register access were missing. So now I am thinking if I should rather only use the fast clock in the final serdes | 11:32 |
| LnnrtS | stage the phy. But before I wanted to ask someone more familiar with this matter if this is promising path or if there is anything else to consider | 11:32 |
| Flea86 | LnnrtS: Define faster clock. Don't forget you may also need a switchable Vcc between 3.3V and 1.8V during that process. | 11:36 |
| Flea86 | I am just a casual litex user myself, though the people who can better answer your question do live here. | 11:37 |
| Flea86 | Suggest sticking around and hopefully someone else may chime in | 11:39 |
| LnnrtS | I am running on ecp with 48MHz sysclock which gives me 24MHz (12MB/s) on the sdio bus. I would like to achieve ideally 32MB/s but 24MB/s (factor 2x) would already be a huge help. The firmware is not really doing much so I figured I'd rather try to keep the sysclock slow | 11:39 |
| LnnrtS | For what I understand I don't need UHS-I mode (so no voltage switch) in that scenario | 11:40 |
| Flea86 | Interesting.. TIL it isn't the card's Vcc that changes, but the data transfer line levels to said card | 11:45 |
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