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| Hammdist | https://github.com/litex-hub/litex-boards/blob/ba86121ea9406830328b588212d95f87a599ed05/litex_boards/platforms/colorlight_5a_75b.py#L315 | 20:13 |
|---|---|---|
| Hammdist | anyone knows if 8.2 is supported? would it work to just build an image for 8.0? | 20:14 |
| Hammdist | this is in relation to colorlight 5a-75b | 20:14 |
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| Hammdist | it seems some of the components are different on the 8.2 | 20:28 |
| Hammdist | the markings on the ethernet phys say 8211FP, not 8211FD (as in the 8.0) | 20:28 |
| Hammdist | as far as I can tell by looking it up, there is no such chip as the 8211FP though | 20:29 |
| Hammdist | is there such a thing as misprints and typos in chip markings? | 20:30 |
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| Hoernchen_ | it appears to work on 8.2, but eth is apparently a bit flaky, and pings get lost | 21:21 |
| Hoernchen_ | it is hard to tell why tho, it might just be general timing issues when building the bitstream | 21:22 |
| Hammdist | timing issues sound like they would affect all versions equally, if that were the case. dunno what it might be though | 21:45 |
| Hoernchen_ | yeah but the problem is that no one is building images for those boards and there have been years of changes | 21:52 |
| Hoernchen_ | the problem is that you can't define false paths that should be ignored so there have always been timing errors, and I don't know if any of that was ever better/worse or matters at all | 21:53 |
| Hammdist | hm. well my design passes timing without errors in nextpnr at speed grade 6 ... I haven't got around to testing it on the colorlight yet, I have only tested it on the lattice versa board and it seemed to work there but there was a strange problem very similar to what you describe (corrupt ethernet packets, i.e., packet loss in the end) | 21:56 |
| Hoernchen_ | mhhmhm | 21:56 |
| Hoernchen_ | interesting | 21:56 |
| Hoernchen_ | see https://github.com/enjoy-digital/colorlite/issues/8 | 21:57 |
| Hoernchen_ | changing the timing parameter didn't improve anything | 21:57 |
| Hoernchen_ | ..but flooding basically "improves" the packet flow | 21:58 |
| Hammdist | so I should try to source the v7 boards, if possible in 2023 q4 | 21:59 |
| Hoernchen_ | one is like 15 bucks so just give it a try | 21:59 |
| Hoernchen_ | but if your design passes timing on the versa.. well, just check it for the colorlight, and if it passes timing it might just work | 22:00 |
| Hoernchen_ | tho if you are seeing the same issues on the versa i guess something might be broken after all | 22:00 |
| Hammdist | yeah I put the same design that passes at speed grade 6 on a 5g part ... it can't be the timing | 22:01 |
| Hammdist | I tried to determine whether the errors in ethernet are rx or tx, and found out that, surprisingly, they are both, though rx is affected to a significantly greater extent than tx. I don't know what more to try. I suspect the lattice ddrs simply can't do rgmii. I will probably be switching to xilinx next - maybe that will work better. | 23:25 |
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