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| MoeIcenowy | _florent_: maybe the reset signal should be synced to oscillator clk domain? | 04:16 |
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| _florent_ | MoeIcenowy: Sorry, I haven't looked at it closely for now, but this is something working on other PLL wrappers (at least Xilinx, Lattice). | 06:15 |
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| josuah | someone I am working with got the Verilog export working! With a few manual edits on the exported varilog though, which I am currently integrating into LiteX so that the out-of-the-box .v works | 19:24 |
| _florent_ | josuah: In fact, the different generator in LiteX (litex_periph_gen/litex_soc_gen) and in the cores (litedram_gen, litepcie_gen, etc...) also have these purpose. As soon as you integrate non trivial cores, you need to specialize the logic/primitives, so it's generally better to generate for a specific vendor/flow. | 20:30 |
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| josuah | _florent_: this might have been a better way to go, if only I was not so stubborn ^_^' | 20:51 |
| josuah | thank you for pinging me back about it | 20:51 |
| josuah | we might have been lucky in the cores we had to play with | 20:53 |
| josuah | anything using a SERDES might be striked out of the generic export | 20:54 |
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| josuah | this is also the decision of the client, and while I am glad to show the various experiments we do in the form of [RFC] pull-requests... | 22:57 |
| josuah | ... I hope this does not interfer with the ongoing work, there is much to do, such as the Amaranth compat layer back-end | 22:58 |
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