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| _florent_ | josuah: yes sure, if you want. I should also open an issue to share more about this. | 06:17 |
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| MoeIcenowy | _florent_: BTW 8192 L2 size seems to be too big for Tang Primer 20K | 09:05 |
| MoeIcenowy | the FPGA seems to be quite lack of BRAM (called BSRAM by Gowin) | 09:05 |
| MoeIcenowy | BTW what's the point of moving self.rst from PLL reset to cd_sys reset? | 09:05 |
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| _florent_ | MoeIcenowy: I indeed reduced L | 09:43 |
| _florent_ | L2 cache size in Linux-on-LiteX-Vexriscv | 09:43 |
| _florent_ | For the reset, the PLL reset is apparently not working correctly, with the previous code, issuing a reset from the BIOS was freezing the SoC | 09:44 |
| _florent_ | this will need to be investigated, for now I did this change to avoid it | 09:44 |
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