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MoeIcenowy | _florent_: BTW I tried to tweak when dqs_re to be asserted, and the read leveling result seems better | 02:03 |
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MoeIcenowy | well it still doesn't pass read leveling... | 02:06 |
MoeIcenowy | trying to deal with Python slicing is weird | 02:30 |
MoeIcenowy | it behavior is so different to Verilog's | 02:30 |
MoeIcenowy | _florent_: BTW on ECP5 is a high sys_clk needed for DDR to work ? | 02:44 |
MoeIcenowy | I start to doubt 252MT/s is too slow for DDR3 | 02:45 |
MoeIcenowy | (but the timing of GW2A is quite bad ... | 02:45 |
MoeIcenowy | even GW5A isn't something good | 02:45 |
MoeIcenowy | well the JEDEC minimum is tCK = 3.3ns (300MHz clk) ... | 03:10 |
MoeIcenowy | thinking about migrating gw2ddrphy to 1:4 instead of 1:2 | 03:42 |
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_florent_ | MoeIcenowy: On ECP5 most of the targets are using 75MHz with DDR3 (so DDR 300) but it’s working fine at l’Eastwood down to 50MHz. trabucayre started adding 1:4 support so it could be worth exchanging together. | 05:48 |
MoeIcenowy | _florent_: I did a quick try for 1:4 and then quick fail :-( | 06:25 |
MoeIcenowy | 300MT/s is also out of JEDEC spec (the JEDEC spec specifies at least 300MHz CK) | 06:26 |
MoeIcenowy | BTW what's the meaning of "bus errors" of the DRAM controller? | 10:17 |
MoeIcenowy | what does it mean when the bus error is now 0 but data error still exist? | 10:18 |
MoeIcenowy | and for the read_latency of phy_settings, is it just used for a hint? | 10:19 |
MoeIcenowy | BTW I start to doubt that the latency of the read codepath on GW2 is kinda like 9.5 sys_clks | 10:26 |
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MoeIcenowy | or 10.5 | 10:30 |
MoeIcenowy | btw what's the difference between BitSlip currently used by ECP5/GW2 with the one in common? | 11:00 |
MoeIcenowy | okay the common BitSlip reduces one cycle of delay | 11:04 |
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josuah | _florent_: you can ignore most pull requests from me if you look at this issue which summarizes everything: https://github.com/litex-hub/zephyr-on-litex-vexriscv/issues/14 | 18:15 |
_florent_ | @josuah: thanks | 19:46 |
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