| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** jevinskie[m] <jevinskie[m]!jevinskie@2a01:4f8:c012:5b7:0:1:0:22> has quit IRC (Quit: Idle timeout reached: 172800s) | 01:38 | |
| *** Degi_ <[email protected]> has joined #litex | 01:46 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 01:48 | |
| *** Degi_ is now known as Degi | 01:48 | |
| *** FabM <[email protected]> has joined #litex | 06:21 | |
| MoeIcenowy | ah someone asked me that is Migen still alive yesterday | 06:35 |
|---|---|---|
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 07:09 | |
| *** TMM_ <[email protected]> has joined #litex | 07:09 | |
| *** cr1901_ <cr1901_!~cr1901@2601:8d:8600:226:bc7f:ccf1:49c0:41ee> has joined #litex | 07:54 | |
| *** cr1901 <cr1901!~cr1901@2601:8d:8600:226:d523:f333:da88:b877> has quit IRC (Ping timeout: 248 seconds) | 07:55 | |
| MoeIcenowy | btw for single chip ddr3 is write leveling not necessary? | 08:47 |
| MoeIcenowy | how does the DEL_VALUE on ECP5 decide the delay value when USER_DEFINED ? | 09:59 |
| _florent_ | MoeIcenowy: For single chip, you can generally use static timings, that’s what’s we are doing on Artix7 (since no ODELAYs) , ECP5 and that’s what is done by some vendors (IIRC Efinix controller has an option for this to save resources) | 10:01 |
| zyp | aren't static timings orthogonal to the number of chips? even for a single chip you need the correct timings, and if you know the correct timings you could use static timings on a multichip system as well… | 10:04 |
| MoeIcenowy | I am still trying to dig out why the GW2DDRPHY ported from ECP5DDRPHY does not wotk | 10:14 |
| MoeIcenowy | work * | 10:14 |
| MoeIcenowy | I now start to think ECP5's DELAYG with p_DEL_MODE="DQS_ALIGNED_X2" is some magic | 10:14 |
| MoeIcenowy | but I cannot understand how this is implemented | 10:14 |
| MoeIcenowy | okay it looks like from the implementation of pack.cc in nextpnr, it's just a fixed delay value? | 10:19 |
| josuah | MoeIcenowy: is that possible that an instance from one device of vendor transposed to another device of another vendor works the same way at all? | 12:05 |
| josuah | oh... maybe you are trying to understand what exactly is portable and what is not, and hence try to guess what these parameters can be doing on one side | 12:07 |
| *** lexano <[email protected]> has quit IRC (Ping timeout: 246 seconds) | 12:08 | |
| _florent_ | @zyp: sorry I was answering for write leveling case: with a single chip and without output delays, adjusting the clk phase and doing a few P&R is generally enough to get it working. For multichip, implementing proper write leveling requires output delays and proper calibration to find the timings. On a deployed and fixed design you can then use static timings but you’ll stil need a version of the design with the calibration to find them. | 13:08 |
| _florent_ | MoeIcenowy: sorry, on my phone and don’t remember the details the GW2DDRPHY but we have also planned to work on it with @trabucayre in the next weeks. | 13:13 |
| MoeIcenowy | josuah: well yes true, and the major structure of them are both similar (and quite different with Xilinx ones) | 14:40 |
| MoeIcenowy | In addition I utilized the .vo files from the PnR tool (which will contain only primitives) to check how the vendor IP does | 14:41 |
| MoeIcenowy | and at least this can show what primitives are being used | 14:41 |
| MoeIcenowy | _florent_: BTW I cannot understand how is ECP5DDRPHY working -- it works at a so low frequency ... | 14:46 |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Ping timeout: 246 seconds) | 15:10 | |
| *** Foxyloxy <Foxyloxy!~foxyloxy@cpc151593-shef16-2-0-cust343.17-1.cable.virginm.net> has quit IRC (Ping timeout: 260 seconds) | 16:17 | |
| *** cr1901_ is now known as cr1901 | 16:57 | |
| josuah | I thought ECP5DDRPHY was a primitive, but no, it's a LiteX class | 17:03 |
| josuah | MoeIcenowy: there is something called FPGA Libraries Reference Guide | 17:06 |
| josuah | which might have documentation for each primitive you can find in ECP5DDRPHY implementation | 17:06 |
| josuah | https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py | 17:07 |
| josuah | https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI2/fpga_library_D311SP3.ashx?document_id=52656 | 17:07 |
| josuah | The ECP5 primitives are listed in there | 17:08 |
| *** Foxyloxy <Foxyloxy!~foxyloxy@cpc151593-shef16-2-0-cust343.17-1.cable.virginm.net> has joined #litex | 17:14 | |
| *** GNUmoon <GNUmoon!~GNUmoon@gateway/tor-sasl/gnumoon> has quit IRC (Ping timeout: 246 seconds) | 18:31 | |
| *** shenki <[email protected]> has quit IRC (Ping timeout: 244 seconds) | 18:32 | |
| *** shenki <[email protected]> has joined #litex | 18:33 | |
| *** GNUmoon <GNUmoon!~GNUmoon@gateway/tor-sasl/gnumoon> has joined #litex | 18:34 | |
| *** MoeIcenowy <MoeIcenowy!~MoeIcenow@2401:c080:1000:445a:5400:4ff:fe31:6509> has quit IRC (Ping timeout: 246 seconds) | 20:55 | |
| *** MoeIcenowy <MoeIcenowy!~MoeIcenow@2401:c080:1000:445a:5400:4ff:fe31:6509> has joined #litex | 21:41 | |
| *** manawyrm <manawyrm!manawyrm@2a01:4f8:212:2e07::81> has quit IRC (Quit: Read error: 2.99792458 x 10^8 meters/second (Excessive speed of light)) | 22:30 | |
| *** manawyrm <[email protected]> has joined #litex | 22:31 | |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 22:31 | |
| *** TMM_ <[email protected]> has joined #litex | 22:32 | |
| *** Foxyloxy <Foxyloxy!~foxyloxy@cpc151593-shef16-2-0-cust343.17-1.cable.virginm.net> has quit IRC (Read error: Connection reset by peer) | 23:03 | |
| *** Foxyloxy <Foxyloxy!~foxyloxy@cpc151593-shef16-2-0-cust343.17-1.cable.virginm.net> has joined #litex | 23:04 | |
| *** shorne <[email protected]> has quit IRC (Ping timeout: 240 seconds) | 23:07 | |
| *** shorne <[email protected]> has joined #litex | 23:08 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!